# US 2014/0191330 A1 · Finfet and method of fabrication

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- Number: US 2014/0191330 A1
- Document ID: US20140191330A1
- Status: Published application
- Kind: A1
- Application number: 13/737,067
- Filed: 2013-01-09
- Published: 2014-07-10
- Earliest claimed: 2013-01-09
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Kangguo Cheng; Thomas N. Adam; Ali Khakifirooz; Alexander Reznicek
- Web page: https://patentgrep.com/patent/US20140191330A1

## CPC

- H10D 86/215: {comprising FinFETs}
- H10D 30/6215: {having multiple independently-addressable gate electrodes}
- H10D 30/6217: {having non-uniform gate electrodes, e.g. gate conductors having varying doping}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10D 86/011: {comprising FinFETs}
- H10P 14/20: of semiconductor materials
- H10P 14/3466: {Crystal orientation}
- H10B 10/12: {comprising a MOSFET load element}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

An improved finFET and method of fabrication is disclosed. Embodiments of the present invention take advantage of the different epitaxial growth rates of {110} and {100} silicon. Fins are formed that have {110} silicon on the fin tops and {100} silicon on the long fin sides (sidewalls). The lateral epitaxial growth rate is faster than the vertical epitaxial growth rate. The resulting merged fins have a reduced merged region in the vertical dimension, which reduces parasitic capacitance. Other fins are formed with {110} silicon on the fin tops and also {110} silicon on the long fin sides. These fins have a slower epitaxial growth rate than the {100} side fins, and remain unmerged in a semiconductor integrated circuit, such as an SRAM circuit.

## Claims

### Claim 1

A semiconductor structure comprising:
a first semiconductor fin disposed on a substrate, wherein the first semiconductor fin comprises a top surface and two sidewall surfaces comprising a {100} crystalline plane, and wherein the first semiconductor fin top surface is comprised of a {110} crystalline plane; and
a second semiconductor fin, wherein the second semiconductor fin comprises a top surface and two sidewall surfaces comprising a non-{100} crystalline plane, and wherein the second semiconductor fin top surface is comprised of a {110} crystalline plane

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the two sidewall surfaces of the second semiconductor fin are comprised of a {111} crystalline plane.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1, wherein the two sidewall surfaces of the second semiconductor fin are comprised of a {110} crystalline plane.

### Claim 4 (depends on 1)

The semiconductor structure of claim 1, wherein the substrate is comprised of an insulator layer, and wherein the substrate is disposed on a semiconductor layer.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1, wherein the substrate is comprised of silicon.

### Claim 6 (depends on 2)

The semiconductor structure of claim 2, further comprising a third semiconductor fin oriented parallel to the first semiconductor fin, and wherein an epitaxial semiconductor region is disposed on the first semiconductor fin and third semiconductor fin.

### Claim 7 (depends on 6)

The semiconductor structure of claim 6, wherein the epitaxial semiconductor region is comprised of silicon.

### Claim 8

An integrated circuit comprising:
a semiconductor substrate having a top surface comprised of a {110} crystalline plane;
a first group of finFET transistors comprising a first set of fins, the first set of fins having fin sidewalls, the first set of fins oriented on the semiconductor substrate such that its fin sidewalls have a {100} crystalline plane; and
a second group of finFET transistors comprising a second set of fins, the second set of fins having fin sidewalls, the second set of fins oriented on the semiconductor substrate such that the fin sidewalls of the second set of fins have a non-{100} crystalline plane.

### Claim 9 (depends on 8)

The integrated circuit of claim 8, wherein the first group of fins are merged and the second group of fins are unmerged.

### Claim 10 (depends on 9)

The integrated circuit of claim 9, wherein the integrated circuit comprises a static random access memory circuit.

### Claim 11 (depends on 10)

The integrated circuit of claim 10, wherein the static random access memory circuit comprises a plurality of memory cell transistors and a plurality of logic transistors, and wherein the plurality of memory cell transistors are comprised of the second set of fins, and wherein the plurality of logic transistors are comprised of the first set of fins.

### Claim 12

A method of fabricating a semiconductor structure comprising forming a first set of fins on a {110} wafer, each fin of the first set of fins having a top surface and two sidewalls, wherein each fin of the first set of fins is oriented with its top oriented parallel to a {110} plane and its sidewalls parallel to a {100} plane, and forming a second set of fins on the {110} wafer, each fin of the second set of fins having two sidewalls, wherein each fin of the second set of fins is oriented with its top oriented parallel to a {110} plane and its sidewalls not oriented to a {100} plane.

### Claim 13 (depends on 12)

The method of claim 12, wherein forming a second set of fins on the {110} wafer, comprises forming fins with sidewalls parallel to a {110} plane.

### Claim 14 (depends on 13)

The method of claim 13, wherein the forming the first set of fins and forming the second set of fins is performed with a sidewall image transfer process.

### Claim 15 (depends on 14)

The method of claim 14, further comprising:
forming a first gate over the first set of fins; and
forming a second gate over the second set of fins.

### Claim 16 (depends on 15)

The method of claim 15, wherein forming the first gate and forming the second gate is performed with a sidewall image transfer process.

### Claim 17 (depends on 13)

The method of claim 13, further comprising:
merging the first set of fins and preserving the second set of fins as unmerged fins.

### Claim 18 (depends on 17)

The method of claim 17, wherein merging the first set of fins comprises forming an epitaxial semiconductor region on the first set of fins and second set of fins.

### Claim 19 (depends on 18)

The method of claim 18, wherein forming the epitaxial semiconductor region on the first set of fins comprises:
growing the epitaxial semiconductor region laterally at a first growth rate; and
growing the epitaxial semiconductor region vertically at a second growth rate, wherein the first growth rate is faster than the second growth rate.

### Claim 20 (depends on 19)

The method of claim 19, wherein the first growth rate ranges from about 1.5 times the second growth rate to about 4 times the second growth rate.