# US 2014/0191329 A1 · Method for producing metal contacts within an integrated circuit, and corresponding integrated circuit

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- Number: US 2014/0191329 A1
- Document ID: US20140191329A1
- Status: Published application
- Kind: A1
- Application number: 14/143,100
- Filed: 2013-12-30
- Published: 2014-07-10
- Earliest claimed: 2013-01-04
- Assignees: STMicroelectronics (Rousset) SAS
- Applicants: STMicroelectronics (Rousset) SAS
- Inventors: Christian Rivero; Roger Delattre
- Web page: https://patentgrep.com/patent/US20140191329A1

## CPC

- H10D 30/794: {comprising conductive materials, e.g. silicided source, drain or gate electrodes}
- H10D 30/0223: {having source and drain regions or source and drain extensions self-aligned to sides of the gate}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 64/01125: {the silicides being formed by chemical reaction with the semiconductor after the contact hole formation}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/258: {characterised by the relative positions of the source or drain electrodes with respect to the gate electrode}
- H10W 20/033: {in openings in dielectrics}
- H10W 20/047: {by introducing additional elements therein}
- H10W 20/083: {the openings being via holes penetrating underlying conductors}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10D 64/0131: {the additional conductive layer comprising a silicide layer formed by the silicidation reaction between the layer of silicon with a metal layer which is not formed by metal implantation}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An integrated circuit includes a MOS transistor having a gate region and source and drain regions separated from the gate region by insulating spacers. At least two metal contact pads respectively contact with two metal silicide regions (for example, a cobalt silicide) which lie within the source and drain regions. The silicide regions are located at the level of lower parts of the two metal contact pads and are separate by a distance from the insulating spacers.

## Claims

### Claim 1

A method, comprising:
forming an orifice in a portion of an integrated circuit, said orifice opening into a zone of a silicon region of the integrated circuit;
forming a nickel-free first metal layer on a side wall of the orifice and on said zone;
forming an electrically conductive barrier layer above the nickel-free first metal layer;
forming a metal silicide from the metal of the nickel-free first metal layer under the barrier layer in contact with the silicon zone; and
filling the orifice with a filling metal covering the electrically conductive barrier layer.

### Claim 2 (depends on 1)

The method according to claim 1, wherein forming the metal silicide comprises performing at least one anneal carried out before the filling of the orifice.

### Claim 3 (depends on 2)

The method according to claim 2, wherein forming the metal silicide comprises performing two successive anneals carried out before the filling of the orifice.

### Claim 4 (depends on 2)

The method according to claim 2, wherein the first metal layer comprises cobalt, and forming the metal silicide comprises forming cobalt monosilicide CoSi.

### Claim 5 (depends on 2)

The method according to claim 2, wherein the first metal layer comprises cobalt, and forming the metal silicide comprises forming cobalt disilicide CoSi2.

### Claim 6 (depends on 1)

The method according to claim 1, wherein forming the metal silicide comprises performing at least one anneal carried out after the filling of the orifice.

### Claim 7 (depends on 6)

The method according to claim 6, wherein forming the metal silicide comprises performing two successive anneals carried out after the filling of the orifice.

### Claim 8 (depends on 6)

The method according to claim 6, wherein the first metal layer comprises cobalt, and forming the metal silicide comprises forming cobalt monosilicide CoSi.

### Claim 9 (depends on 6)

Method according to claim 6, wherein the first metal layer comprises cobalt, and forming the metal silicide comprises forming cobalt disilicide CoSi2.

### Claim 10 (depends on 1)

The method according to claim 1, wherein forming the electrically conductive barrier layer comprises forming a layer of titanium nitride TiN, and the filling metal comprises tungsten.

### Claim 11 (depends on 1)

The method according to claim 1, wherein forming the first metal layer and forming the barrier layer also comprise covering the first integrated circuit portion with the first metal layer surmounted by the barrier layer, and wherein filling the orifice also comprises covering the first metal layer surmounted by the barrier layer with a layer of the filling metal to form a stack of layers, and removing the stack of layers from the first portion outside the filled first orifice.

### Claim 12 (depends on 1)

The method according to claim 1, wherein the through-orifice is formed opening at depth into the zone of the silicon region, and forming the metal silicide comprises forming metal silicide having a U-shape between the silicon region and the barrier layer.

### Claim 13

An integrated circuit, comprising:
at least one metal contact arranged in a first portion of the integrated circuit and having:
a central metal region covered laterally and in a lower part thereof with an electrically conductive barrier layer, and
a nickel-free outer metal layer covering the lateral part of the barrier layer,
said metal contact coming in contact with a silicided region essentially located under the barrier layer at the level of the lower part of the metal contact and comprising a nickel-free metal silicide.

### Claim 14 (depends on 13)

The integrated circuit of claim 13, wherein the integrated circuit includes at least one MOS transistor having a gate region and source and drain regions separated from the gate region by insulating spacers, and the at least one metal contact comprises at two metal contacts in contact with silicided regions of the source and drain regions, said silicided regions located at the level of lower parts of the two metal contacts and at a distance from the insulating spacers.

### Claim 15 (depends on 13)

The integrated circuit according to claim 13, wherein each contact has a central metal region covered laterally and in its lower part with an electrically conductive barrier layer, and an outer metal layer covering the lateral part of the barrier layer, the silicided region being essentially located under the barrier layer of the corresponding metal contact.

### Claim 16 (depends on 15)

The integrated circuit according to claim 15, wherein the outer metal layer comprises cobalt.

### Claim 17 (depends on 15)

The integrated circuit according to claim 15, wherein the barrier layer comprises titanium nitride and the metal of the central region is tungsten.

### Claim 18 (depends on 14)

The integrated circuit according to claim 14, wherein the silicided region is essentially located under the metal contact.

### Claim 19 (depends on 14)

The integrated circuit according to claim 14, wherein the silicided region has a U-shape and is essentially located around the lower part of the metal contact.

### Claim 20 (depends on 14)

The integrated circuit according to claim 14, wherein the silicided region comprises one of cobalt monosilicide CoSi or cobalt disilicide CoSi2.