# US 2014/0191328 A1 · Semiconductor memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0191328 A1 - Document ID: US20140191328A1 - Status: Published application - Kind: A1 - Application number: 14/133,263 - Filed: 2013-12-18 - Published: 2014-07-10 - Earliest claimed: 2013-01-10 - Assignees: Fujitsu Semiconductor Limited - Applicants: Fujitsu Semiconductor Limited - Inventors: Tomoya TSURUTA; Ryo Tanabe - Web page: https://patentgrep.com/patent/US20140191328A1 ## CPC - H10D 89/10: Integrated device layouts - H10B 10/12: {comprising a MOSFET load element} - H10B 10/18: {Peripheral circuit regions} - H10B 12/50: {Peripheral circuit region structures} - H10B 41/40: characterised by the peripheral circuit region - H10D 84/0188: {Manufacturing their isolation regions} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/859: {comprising both N-type and P-type wells, e.g. twin-tub} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A semiconductor memory device has a memory cell array having memory cells, each including first and second conduction type transistors, a peripheral circuit having the first and second conduction type transistors, a first conduction type memory cell array well region within the memory cell array region, a second conduction type memory cell array well region within the first conduction type memory cell array well region, a first conduction type peripheral circuit well region within the peripheral circuit region, a second conduction type peripheral circuit well region within the first conduction type peripheral circuit well region, and a second conduction type isolation region between the first conduction type memory cell array well region and the first conduction type peripheral circuit well region. At least a portion of first conduction type transistors of first conduction type transistors of the peripheral circuit is formed in the second conduction type isolation region. ## Claims ### Claim 1 A semiconductor memory device, comprising: a memory cell array in which are disposed a plurality of memory cells, each including a first conduction type transistor and a second conduction type transistor; a peripheral circuit which includes the first conduction type transistor and the second conduction type transistor, and which controls access to memory cells in the memory cell array; a first conduction type memory cell array well region, which is within the region of the memory cell array, and in which are formed the second conduction type transistors of the plurality of memory cells; a second conduction type memory cell array well region, which is within the first conduction type memory cell array well region, and in which are formed the first conduction type transistors of the plurality of memory cells; a first conduction type peripheral circuit well region, which is within the region of the peripheral circuit, and in which is formed the second conduction type transistor of the peripheral circuit; a second conduction type peripheral circuit well region, which is within the first conduction type peripheral circuit well region, and in which is formed the first conduction type transistor of the peripheral circuit; and a second conduction type isolation region, which is disposed between the first conduction type memory cell array well region and the first conduction type peripheral circuit well region, wherein at least a portion of first conduction type transistors of first conduction type transistors of the peripheral circuit is formed in the second conduction type isolation region. ### Claim 2 (depends on 1) The semiconductor memory device according to claim 1, wherein at least one of the portion of first conduction type transistors formed in the second conduction type isolation region includes a first conduction type transistor, which is conductive in an operation state other than a readout operation or a write operation. ### Claim 3 (depends on 2) The semiconductor memory device according to claim 2, wherein the memory cell array includes a plurality of word lines connected to the plurality of memory cells, the peripheral circuit includes a word driving circuit which is an inverter including the first conduction type transistor and the second conduction type transistor and which drives a selected word line, and the first conduction type transistor which is conductive in an operation state other than a readout operation or a write operation includes the first conduction type transistor within the word driving circuit. ### Claim 4 (depends on 1) The semiconductor memory device according to claim 1, wherein at least one of the portion of first conduction type transistors formed in the second conduction type isolation region includes a first conduction type transistor, the source and drain of which are at the same potential in an operation state other than a readout operation or a write operation. ### Claim 5 (depends on 4) The semiconductor memory device according to claim 4, wherein the memory cell array includes a plurality of bit lines connected to a plurality of memory cells, the peripheral circuit includes a column selection circuit including a first conduction type transistor which connects at least one selected bit line among the plurality of bit lines to a data bus line, and the first conduction type transistor, the source and drain of which are at the same potential in an operation state other than a readout operation or a write operation, includes a first conduction type transistor within the column selection circuit. ### Claim 6 (depends on 4) The semiconductor memory device according to claim 4, wherein the column selection circuit includes a transfer gate circuit between the bit line and a data bus line, and the first conduction type transistor, the source and drain of which are at the same potential in an operation state other than a readout operation or a write operation, includes a first conduction type transistor within the transfer gate circuit. ### Claim 7 A semiconductor memory device, comprising: a memory cell array in which are disposed a plurality of memory cells, each including a first conduction type transistor and a second conduction type transistor; a peripheral circuit, which includes the first conduction type transistor and the second conduction type transistor, and which controls access to memory cells in the memory cell array; a first conduction type memory cell array well region, which is within the region of the memory cell array, and in which are formed the second conduction type transistors of the plurality of memory cells; a second conduction type memory cell array well region, which is within the first conduction type memory cell array well region, and in which are formed a first conduction type transistors of the plurality of memory cells; a first conduction type peripheral circuit well region, which is within the region of the peripheral circuit, and in which is formed the second conduction type transistor of the peripheral circuit; a second conduction type peripheral circuit well region, which is within the first conduction type peripheral circuit well region, and in which is formed the first conduction type transistor of the peripheral circuit; and a second conduction type isolation region, which is disposed between the first conduction type memory cell array well region and the first conduction type peripheral circuit well region, wherein at least a portion of second conduction type transistors of second conduction type transistors of the peripheral circuit is formed in a peripheral region of the first conduction type memory cell array well region surrounding the plurality of second conduction type memory cell array well regions in the region of the memory cell array. ### Claim 8 (depends on 7) The semiconductor memory device according to claim 7, wherein the memory cell array includes a plurality of bit lines connected to a plurality of memory cells, the peripheral circuit includes a column selection circuit including a second conduction type transistor which connects at least one selected bit line among the plurality of bit lines to a first data bus line, and the portion of second conduction type transistors formed in the peripheral region of the first conduction type memory cell array well region includes the second conduction type transistor in the column selection circuit. ### Claim 9 (depends on 8) The semiconductor memory device according to claim 8, wherein the column selection circuit includes, in addition to the second conduction type transistor which connects a selected bit line to a first data bus line, a first conduction type transistor which connects the selected bit line to a second data bus line. ### Claim 10 (depends on 9) The semiconductor memory device according to claim 9, wherein the first conduction type transistor in the column selection circuit is formed in the second conduction type isolation region. ### Claim 11 (depends on 1) The semiconductor memory device according to claim 1, wherein different back gate voltages are supplied to the first conduction type memory cell array well region and to the first conduction type peripheral circuit well region. ### Claim 12 (depends on 11) The semiconductor memory device according to claim 11, wherein a first back gate voltage is supplied to the first conduction type memory cell array well region, and a second back gate voltage at positive potential lower than the first back gate voltage, is supplied to the first conduction type peripheral circuit well region. ### Claim 13 (depends on 1) The semiconductor memory device according to claim 1, wherein different back gate voltages are supplied to the second conduction type memory cell array well region and to the second conduction type peripheral circuit well region. ### Claim 14 (depends on 13) The semiconductor memory device according to claim 13, wherein a third back gate voltage is supplied to the second conduction type memory cell array well region, and a fourth back gate voltage at negative potential less negative than the third back gate voltage, is supplied to the second conduction type peripheral circuit well region. ### Claim 15 (depends on 14) The semiconductor memory device according to claim 14, wherein a fifth back gate voltage at potential less negative than the fourth back gate voltage is supplied to the second conduction type isolation region. ### Claim 16 (depends on 7) The semiconductor memory device according to claim 7, wherein different back gate voltages are supplied to the first conduction type memory cell array well region and to the first conduction type peripheral circuit well region. ### Claim 17 (depends on 16) The semiconductor memory device according to claim 16, wherein a first back gate voltage is supplied to the first conduction type memory cell array well region, and a second back gate voltage at positive potential lower than the first back gate voltage, is supplied to the first conduction type peripheral circuit well region. ### Claim 18 (depends on 7) The semiconductor memory device according to claim 7, wherein different back gate voltages are supplied to the second conduction type memory cell array well region and to the second conduction type peripheral circuit well region. ### Claim 19 (depends on 18) The semiconductor memory device according to claim 18, wherein a third back gate voltage is supplied to the second conduction type memory cell array well region, and a fourth back gate voltage at negative potential less negative than the third back gate voltage, is supplied to the second conduction type peripheral circuit well region. ### Claim 20 (depends on 19) The semiconductor memory device according to claim 19, wherein a fifth back gate voltage at potential less negative than the fourth back gate voltage is supplied to the second conduction type isolation region.