# US 2014/0191322 A1 · Silicon-on-insulator heat sink

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- Number: US 2014/0191322 A1
- Document ID: US20140191322A1
- Status: Published application
- Kind: A1
- Application number: 13/738,532
- Filed: 2013-01-10
- Published: 2014-07-10
- Earliest claimed: 2013-01-10
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Alan B. BOTULA; Alvin J. JOSEPH; James A. SLINKMAN; Randy L. WOLF
- Web page: https://patentgrep.com/patent/US20140191322A1

## CPC

- H10W 40/00: Arrangements for thermal protection or thermal control (integrated devices comprising arrangements for thermal protection H10D89/60)
- H10D 30/0212: {using self-aligned silicidation}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/711: {having floating bodies}
- H10D 86/01: Manufacture or treatment
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10W 40/228: {the projecting parts being wire-shaped or pin-shaped}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An approach for sinking heat from a transistor is provided. A method includes forming a substrate contact extending from a first portion of a silicon-on-insulator (SOI) island to a substrate. The method also includes forming a transistor in a second portion of the SOI island. The method further includes electrically isolating the substrate contact from the transistor by doping the first portion of the SOI island.

## Claims

### Claim 1

A method of manufacturing a semiconductor structure, comprising:
forming a substrate contact extending from a first portion of a silicon-on-insulator (SOI) island to a substrate;
forming a transistor in a second portion of the SOI island; and
electrically isolating the substrate contact from the transistor by doping the first portion of the SOI island.

### Claim 2 (depends on 1)

The method of claim 1, wherein the forming the substrate contact comprises:
etching a trench through the first portion of the SOI island and through a buried insulator layer, wherein the trench extends to or into the substrate; and
filling the trench with a material, wherein a thermal conductivity of the material is greater than a thermal conductivity of the buried insulator layer.

### Claim 3 (depends on 1)

The method of claim 1, wherein the doping the first portion of the SOI island comprises implanting ions of a first type in the first portion of the SOI island.

### Claim 4 (depends on 3)

The method of claim 3, wherein:
the forming the transistor in the second portion of the SOI island comprises forming a source region and a drain region of the transistor in the second portion of the SOI island by implanting ions of a second type in the source region and the drain region; and
the first type of ions is opposite from the second type of ions.

### Claim 5 (depends on 4)

The method of claim 4, further comprising:
forming a block on the first portion of the SOI island and extending over an interface between the first portion of the SOI island and the second portion of the SOI island; and
forming silicide on surfaces of the source region and the drain region that are unmasked by the block.

### Claim 6 (depends on 1)

The method of claim 1, further comprising:
forming a first electrical contact on a source region of the transistor;
forming a second electrical contact on the substrate contact; and
forming a metal layer on and electrically connecting the first electrical contact and the second electrical contact.

### Claim 7

A method of manufacturing a semiconductor device, comprising:
defining an island in a semiconductor layer of a silicon-on-insulator (SOI) wafer;
forming a trench through the island and an underlying buried insulator layer, wherein the trench extends to or into a substrate under the buried insulator layer;
forming a substrate contact in the trench, wherein the substrate contact comprises a material having a thermal conductivity that is greater than a thermal conductivity of the buried insulator layer;
forming a transistor in the island; and
electrically isolating the substrate contact from the transistor by doping a portion of the island.

### Claim 8 (depends on 7)

The method of claim 7, wherein:
the forming the transistor comprises forming a source region and a drain region doped with a first type of impurity in the island;
the electrically isolating the substrate contact from the transistor comprises doping the portion of the island with a second type of impurity; and
the second type of impurity is different than the first type of impurity.

### Claim 9 (depends on 7)

The method of claim 7, wherein the doping the portion of the island comprises doping a region of the island that includes the substrate contact.

### Claim 10 (depends on 7)

The method of claim 7, wherein the doping the portion of the island comprises doping a region of the island that is between the substrate contact and a source region and a drain region of the transistor.

### Claim 11

A semiconductor structure, comprising:
a substrate;
a buried insulator layer on the substrate;
an island of a semiconductor layer on the buried insulator layer;
a substrate contact extending from a first area of the island to the substrate through the buried insulator layer; and
a transistor in a second area of the island, wherein:
the substrate contact comprises a material having a thermal conductivity that is greater than a thermal conductivity of the buried insulator layer; and
the substrate contact is electrically isolated from the transistor.

### Claim 12 (depends on 11)

The structure of claim 11, wherein the first area of the island directly contacts the second area of the island.

### Claim 13 (depends on 11)

The structure of claim 11, wherein the substrate, the island, and the substrate contact all comprise the material.

### Claim 14 (depends on 13)

The structure of claim 13, wherein the material is silicon.

### Claim 15 (depends on 11)

The structure of claim 11, further comprising a doped region in the island that electrically isolates the substrate contact from the transistor.

### Claim 16 (depends on 15)

The structure of claim 15, wherein the doped region surrounds the substrate contact.

### Claim 17 (depends on 15)

The structure of claim 15, wherein the doped region is between the substrate contact and a source region and a drain region of the transistor.

### Claim 18 (depends on 17)

The structure of claim 17, wherein the doped region comprises a body contact of a gate of the transistor.

### Claim 19 (depends on 15)

The structure of claim 15, wherein:
the doped region comprises a first type of impurity; and
a source region and a drain region of the transistor comprise a second type of impurity that is different than the first type of impurity.

### Claim 20 (depends on 15)

The structure of claim 15, wherein the doped region directly contacts the source region of the transistor.