# US 2014/0191321 A1 · Finfet with dielectric isolation by silicon-on-nothing and method of fabrication

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- Number: US 2014/0191321 A1
- Document ID: US20140191321A1
- Status: Published application
- Kind: A1
- Application number: 13/737,002
- Filed: 2013-01-09
- Published: 2014-07-10
- Earliest claimed: 2013-01-09
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporatation
- Inventors: Kangguo Cheng; Balasubramanian S. Haran; Shom Ponoth; Theodorus Eduardus Standaert; Tenko Yamashita
- Web page: https://patentgrep.com/patent/US20140191321A1

## CPC

- H10B 12/36: {the transistor being a FinFET}
- H10D 86/011: {comprising FinFETs}
- H10D 86/215: {comprising FinFETs}
- H10P 90/1906: {Preparing SOI wafers}
- H10P 90/1908: {using silicon implanted buried insulating layers, e.g. oxide layers [SIMOX]}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/061: {using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An improved finFET and method of fabrication using a silicon-on-nothing process flow is disclosed. Nitride spacers protect the fin sides during formation of cavities underneath the fins for the silicon-on-nothing (SON) process. A flowable oxide fills the cavities to form an insulating dielectric layer under the fins.

## Claims

### Claim 1

A semiconductor structure comprising:
a semiconductor substrate;
an insulator layer disposed over the semiconductor substrate;
a plurality of semiconductor fins disposed on the insulator layer; and
a plurality of embedded spacers disposed in the insulator layer adjacent to each fin.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the insulator layer has a first thickness in an under-fin region located directly below each fin of the plurality of semiconductor fins and a second thickness in an inter-fin region located between each fin of the plurality of semiconductor fins, wherein the first thickness is greater than the second thickness.

### Claim 3 (depends on 2)

The semiconductor structure of claim 2, wherein the insulator layer in the under-fin region extends above the insulator layer in the inter-fin region.

### Claim 4 (depends on 3)

The semiconductor structure of claim 3, wherein the insulator layer in the under-fin region extends below the insulator layer in the inter-fin region.

### Claim 5 (depends on 2)

The semiconductor structure of claim 2, further comprising a shallow trench isolation region disposed on the semiconductor substrate in the inter-fin region.

### Claim 6 (depends on 4)

The semiconductor structure of claim 4, wherein the first thickness is between 2 times to 4 times greater than the second thickness.

### Claim 7 (depends on 1)

The semiconductor structure of claim 1, wherein the embedded spacers are comprised of nitride and the insulator layer is comprised of oxide.

### Claim 8 (depends on 1)

The semiconductor structure of claim 1, wherein the embedded spacers are comprised of nitride and the insulator layer is comprised of spin-on glass.

### Claim 9 (depends on 1)

The semiconductor structure of claim 1, further comprising a gate region disposed thereon.

### Claim 10 (depends on 9)

The semiconductor structure of claim 9, wherein the gate region is comprised of polysilicon.

### Claim 11 (depends on 9)

The semiconductor structure of claim 9, wherein the gate region is comprised of metal.

### Claim 12 (depends on 9)

The semiconductor structure of claim 9, further comprising an epitaxial silicon region disposed on, and in direct physical contact with the plurality of semiconductor fins.

### Claim 13

A method of forming a semiconductor structure, comprising:
forming a sacrificial layer on a semiconductor substrate;
forming fins on the sacrificial layer;
forming a shallow trench isolation region on the semiconductor substrate, wherein the shallow trench isolation region is disposed in between each fin;
forming spacers on the fins;
recessing the shallow trench isolation region;
removing the sacrificial layer, thereby forming a void in the semiconductor structure;
depositing an insulator layer in the void, wherein the insulator layer partially covers the spacers, leaving an exposed portion of the spacers; and
removing the exposed portion of the spacers.

### Claim 14 (depends on 13)

The method of claim 13, further comprising growing an epitaxial region directly on the fins.

### Claim 15 (depends on 13)

The method of claim 13, wherein forming the sacrificial layer on the semiconductor substrate comprises forming a SiGe layer.

### Claim 16 (depends on 13)

The method of claim 13, further comprising performing a densification anneal after depositing the insulator layer in the void.

### Claim 17 (depends on 16)

The method of claim 16, wherein the performing a densification anneal comprises performing an anneal at a temperature ranging from about 500 degrees Celsius to about 800 degrees Celsius.

### Claim 18 (depends on 16)

The method of claim 16, wherein the performing a densification anneal comprises performing an anneal at a temperature ranging from about 900 degrees Celsius to about 1100 degrees Celsius.

### Claim 19 (depends on 13)

The method of claim 13, wherein depositing the insulator layer in the void comprises depositing a flowable oxide.

### Claim 20 (depends on 13)

The method of claim 13, wherein depositing the insulator layer in the void comprises depositing spin-on glass.

### Claim 21 (depends on 13)

The method of claim 13, wherein depositing the insulator in the void is performed with atomic layer deposition.

### Claim 22 (depends on 13)

The method of claim 13, wherein depositing the insulator in the void is performed with low-pressure chemical vapor deposition.

### Claim 23

A method of forming a semiconductor structure, comprising:
forming fins on a semiconductor substrate, the fins having sides;
forming spacers on the sides of each fin;
forming a mask region on a first group of fins, and leaving a second group of fins unmasked;
forming a cavity in the semiconductor substrate between each of the unmasked fins;
expanding each cavity between each of the unmasked fins with an undercut etch;
filling each cavity between each of the unmasked fins with an insulator material;
forming a cavity in the semiconductor substrate between each of the first group of fins;
expanding each cavity between each of the first group of fins with an undercut etch; and
filling each cavity between each of the first group of fins with an insulator material.

### Claim 24 (depends on 23)

The method of claim 23, wherein filling each cavity between each of the unmasked fins with an insulator material and filling each cavity between each of the first group of fins with an insulator material comprises depositing flowable oxide.

### Claim 25 (depends on 23)

The method of claim 23, wherein filling each cavity between each of the unmasked fins with an insulator material and filling each cavity between each of the first group of fins with an insulator material comprises depositing spin-on glass.

### Claim 26 (depends on 23)

The method of claim 23, wherein filling each cavity between each of the unmasked fins with an insulator material and filling each cavity between each of the first group of fins with an insulator material is performed via atomic layer deposition.

### Claim 27 (depends on 23)

The method of claim 23, wherein filling each cavity between each of the unmasked fins with an insulator material and filling each cavity between each of the first group of fins with an insulator material is performed via low-pressure chemical vapor deposition.

### Claim 28 (depends on 23)

The method of claim 23, wherein forming a mask region on the first group of fins comprises depositing a nitride region.

### Claim 29 (depends on 23)

The method of claim 23, wherein forming a mask region on the first group of fins comprises depositing an amorphous carbon region.