# US 2014/0191320 A1 · Crystalline thin-film transistor

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- Number: US 2014/0191320 A1
- Document ID: US20140191320A1
- Status: Published application
- Kind: A1
- Application number: 13/736,534
- Filed: 2013-01-08
- Published: 2014-07-10
- Earliest claimed: 2013-01-08
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Bahman Hekmatshoartabari; Ning Ll; Devendra K. Sadana; Davood Shahrjerdi
- Web page: https://patentgrep.com/patent/US20140191320A1

## CPC

- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/0323: {comprising monocrystalline silicon}
- H10D 30/67: Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)}
- H10D 30/6731: {Top-gate only TFTs}
- H10D 30/6744: {Monocrystalline silicon}
- H10D 30/6745: {Polycrystalline or microcrystalline silicon}
- H10H 20/062: {Light-emitting semiconductor devices having field effect type light-emitting regions, e.g. light-emitting High-Electron Mobility Transistors}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS

## Abstract

A method for forming a thin film transistor includes joining a crystalline substrate to an insulating substrate. A doped layer is deposited on the crystalline substrate, and the doped layer is patterned to form source and drain regions. The crystalline substrate is patterned to form an active area such that a conductive channel is formed in the crystalline substrate between the source and drain regions. A gate stack is formed between the source and drain regions, and contacts are formed to the source and drain regions and the gate stack through a passivation layer.

## Claims

### Claim 1

A method for forming a thin film transistor, comprising:
joining a crystalline substrate to an insulating substrate;
depositing a doped layer on the crystalline substrate;
patterning the doped layer to form source and drain regions;
patterning the crystalline substrate to form an active area such that a conductive channel is formed in the crystalline substrate between the source and drain regions;
forming a gate stack between the source and drain regions; and
forming contacts to the source and drain regions and the gate stack through a passivation layer.

### Claim 2 (depends on 1)

The method as recited in claim 1, wherein joining a crystalline substrate includes forming the insulating layer on a thick crystalline substrate and removing a portion of the thick crystalline substrate to form a thin crystalline layer for the crystalline substrate joined to the insulating substrate.

### Claim 3 (depends on 2)

The method as recited in claim 2, wherein removing includes cleaving or etching the thick substrate.

### Claim 4 (depends on 1)

The method as recited in claim 1, wherein depositing a doped layer on the crystalline substrate includes depositing the doped layer by a plasma enhanced chemical vapor deposition process having a deposition temperature less than 250 degrees C.

### Claim 5 (depends on 1)

The method as recited in claim 1, wherein the method is performed in its entirety without exceeding 250 degrees C.

### Claim 6 (depends on 1)

The method as recited in claim 1, wherein forming a gate stack includes forming a high dielectric constant (high-K) gate dielectric and a metal gate conductor.

### Claim 7

A method for forming a thin film transistor for displays, comprising:
joining a crystalline substrate to an insulating substrate;
depositing a doped layer on the crystalline substrate;
patterning the doped layer to form source and drain regions;
patterning the crystalline substrate to form an active area such that a conductive channel is formed in the crystalline substrate between the source and drain regions;
forming a gate stack between the source and drain regions;
forming contacts to the source and drain regions and the gate stack through a first passivation layer;
forming one or more metallization layers to provide lines for connecting components; and
depositing and patterning a transparent conductor on the insulating substrate to form pixel electrodes.

### Claim 8 (depends on 7)

The method as recited in claim 7, wherein joining a crystalline substrate includes forming the insulating layer on a thick crystalline substrate and removing a portion of the thick crystalline substrate to form a thin crystalline layer for the crystalline substrate joined to the insulating substrate.

### Claim 9 (depends on 8)

The method as recited in claim 8, wherein removing includes cleaving or etching the thick substrate.

### Claim 10 (depends on 7)

The method as recited in claim 7, wherein depositing a doped layer on the crystalline substrate includes depositing the doped layer by a plasma enhanced chemical vapor deposition process having a deposition temperature less than 250 degrees C.

### Claim 11 (depends on 7)

The method as recited in claim 7, wherein the method is performed in its entirety without exceeding 250 degrees C.

### Claim 12 (depends on 7)

The method as recited in claim 7, wherein forming a gate stack includes forming a high dielectric constant (high-K) gate dielectric and a metal gate conductor.

### Claim 13 (depends on 7)

The method as recited in claim 7, wherein depositing and patterning a transparent conductor on the insulating substrate to form pixel electrodes includes forming electroluminescent material on the electrodes to form a light emitting diode pixel.

### Claim 14 (depends on 7)

The method as recited in claim 7, wherein the pixel electrodes are employed in a liquid crystal display.

### Claim at position 15

-21. (canceled)

### Claim 22 (depends on 1)

The method of claim 1, wherein the doped layer that is deposited on the crystalline substrate is nanocrystalline silicon or microcrystalline silicon.

### Claim 23 (depends on 7)

The method of claim 7, wherein the doped layer that is deposited on the crystalline substrate is nanocrystalline silicon or microcrystalline silicon.

### Claim 24 (depends on 1)

The method of claim 1, wherein the method is performed in its entirety without exceeding 200 degrees C.

### Claim 25 (depends on 7)

The method of claim 7, wherein the method is performed in its entirety without exceeding 200 degrees C.

### Claim 26 (depends on 1)

The method of claim 1 further comprising forming a contact form the drain region to an electrode of a pixel of a display, wherein the thin film transistor is a driver device for the pixel of the display.

### Claim 27 (depends on 7)

The method of claim 7, wherein the thin film transistor is a driver device for a pixel of the display.