# US 2014/0191319 A1 · Finfet compatible diode for esd protection

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- Number: US 2014/0191319 A1
- Document ID: US20140191319A1
- Status: Published application
- Kind: A1
- Application number: 13/733,943
- Filed: 2013-01-04
- Published: 2014-07-10
- Earliest claimed: 2013-01-04
- Assignees: Globalfoundries Inc.; International Business Machines Corporation
- Applicants: International Business Machines Corporation; Globalfoundries, Inc.
- Inventors: Kangguo Cheng; Shom Ponoth; Balasubramanian Pranatharthiharan; Theodorus Eduardus Standaert; Tenko Yamashita; Robert J. Miller
- Web page: https://patentgrep.com/patent/US20140191319A1

## CPC

- H10D 86/011: {comprising FinFETs}
- H10D 8/00: Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00)
- H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors}
- H10D 86/215: {comprising FinFETs}
- H10D 89/611: {using diodes as protective elements}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A diode for integration with finFET devices is disclosed. An in-situ doped epitaxial silicon region is grown on the cathode or anode of the diode to increase the surface area of the junction and overall silicon volume for improved heat dissipation during an ESD event.

## Claims

### Claim 1

A semiconductor diode comprising,
an N− region;
an L-shaped P− region formed within the N− region, wherein the L-shaped P− region forms an L-shaped junction with the N− region; and
a P+ region disposed above and alongside the P− region.

### Claim 2 (depends on 1)

The diode of claim 1, wherein the P+ region is an in-situ doped epitaxial region.

### Claim 3 (depends on 2)

The diode of claim 2, wherein the P+ region comprises a plurality of boron dopants.

### Claim 4 (depends on 2)

The diode of claim 2, further comprising a polysilicon region disposed on the N− region.

### Claim 5 (depends on 4)

The diode of claim 4, further comprising a nitride region disposed over the N− region, the nitride region in direct physical contact with, and completely covering one side of the polysilicon region.

### Claim 6 (depends on 3)

The diode of claim 3, wherein the P+ region has a dopant concentration ranging from about 1E20 atoms per cubic centimeter to about 1E21 atoms per cubic centimeter.

### Claim 7 (depends on 1)

The diode of claim 1, wherein the L-shaped junction has a height equal to the height of the N− region.

### Claim 8 (depends on 7)

The diode of claim 7, wherein the L-shaped junction has a length that is longer than the height of the N− region.

### Claim 9

A semiconductor structure, comprising:
a first silicon region;
an insulator region disposed over the first silicon region;
a diode, the diode comprising:
a second silicon region disposed over the insulator region;
an N+ region formed in the second silicon region;
an N− region formed in the second silicon region and disposed adjacent to the N+ region;
an L-shaped P− region formed within the N− region, wherein the L-shaped P− region forms an L-shaped junction with the N− region;
a P+ region disposed above and alongside the P− region; and
a finFET adjacent to the diode.

### Claim 10 (depends on 9)

The semiconductor structure of claim 9, wherein the finFET comprises a plurality of fins having a fin height equal to the height of the N+ region.

### Claim 11 (depends on 9)

The semiconductor structure of claim 9, further comprising:
a first contact disposed on the N+ region; and
a second contact disposed on the P+ region.

### Claim 12 (depends on 11)

The semiconductor structure of claim 11, further comprising a third contact on a gate region of the finFET.

### Claim 13

A method of forming a diode, comprising:
forming a silicon-on-insulator region;
forming a polysilicon region on the silicon-on-insulator region;
depositing a nitride layer over the silicon-on-insulator region;
forming an N+ region in the silicon-on-insulator region;
removing a portion of the nitride layer to form an exposed portion of the silicon-on-insulator region;
forming an in-situ P-doped epitaxial layer on the exposed portion of the silicon-on-insulator region;
performing an activation anneal; and
forming a first contact over the N+ region and a second contact over the in-situ P-doped epitaxial layer.

### Claim 14 (depends on 13)

The method of claim 13, further comprising forming an N well on the silicon-on-insulator region.

### Claim 15 (depends on 13)

The method of claim 13, wherein forming an N+ region comprises forming an N+ region having a dopant concentration ranging from about 1E20 atoms per cubic centimeter to about 1E21 atoms per cubic centimeter.

### Claim 16 (depends on 13)

The method of claim 13, wherein depositing a nitride layer comprises depositing a nitride layer having a thickness ranging from about 10 nanometers to about 30 nanometers.

### Claim 17 (depends on 13)

The method of claim 13, wherein forming an in-situ P-doped epitaxial layer on the exposed portion of the silicon-on-insulator region comprises adding a plurality of boron dopants.

### Claim 18 (depends on 13)

The method of claim 13, wherein forming an in-situ P-doped epitaxial layer on the exposed portion of the silicon-on-insulator region comprises adding a plurality of phosphorus dopants.

### Claim 19 (depends on 17)

The method of claim 17, wherein forming an in-situ P-doped epitaxial layer comprises forming an epitaxial layer having a dopant concentration ranging from about 1E17 atoms per cubic centimeter to about 1E18 atoms per cubic centimeter.

### Claim 20 (depends on 13)

The method of claim 13, wherein performing an activation anneal comprises performing an activation anneal at a temperature ranging from about 900 degrees Celsius to about 1100 degrees Celsius for a time ranging from about 3 seconds to about 60 seconds.