# US 2014/0191318 A1 · Complementary metal oxide semiconductor field effect transistor, metal oxide semiconductor field effect transistor and manufacturing method thereof

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- Number: US 2014/0191318 A1
- Document ID: US20140191318A1
- Status: Published application
- Kind: A1
- Application number: 13/738,934
- Filed: 2013-01-10
- Published: 2014-07-10
- Earliest claimed: 2013-01-10
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: Chien-Ting Lin; Shih-Hung Tsai
- Web page: https://patentgrep.com/patent/US20140191318A1

## CPC

- H10D 30/0229: {forming drain regions and lightly-doped drain [LDD] simultaneously, e.g. using implantation through a T-shaped mask}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/853: {comprising FinFETs}
- H10D 86/011: {comprising FinFETs}
- H10D 86/215: {comprising FinFETs}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A complementary metal oxide semiconductor field-effect transistor (MOSFET) includes a substrate, a first MOSFET and a second MOSFET. The first MOSFET is disposed on the substrate within a first transistor region and the second MOSFET is disposed on the substrate within a second transistor region. The first MOSFET includes a first fin structure, two first lightly-doped regions, two first doped regions and a first gate structure. The first fin structure includes a first body portion and two first epitaxial portions, wherein each of the first epitaxial portions is disposed on each side of the first body portion. A first vertical interface is between the first body portion and each of the first epitaxial portions so that the first-lightly doped region is able to be uniformly distributed on an entire surface of each first vertical interface.

## Claims

### Claim 1

A complementary metal oxide semiconductor field-effect transistor (MOSFET) comprising:
a substrate comprising a first transistor region and a second transistor region;
a first MOSFET disposed in the first transistor region, wherein the first MOSFET comprises:
a first fin structure comprising a first body portion and two first epitaxial portions, wherein the first epitaxial portions are respectively disposed on each side of the first body portion, and a first vertical interface is interposed between the first body portion and each of the first epitaxial portions;
two first lightly-doped regions respectively and uniformly formed on each of the entire first vertical interface;
two first doped regions respectively disposed in each of the first epitaxial portions; and
a first gate structure overlying the first body portion; and
a second MOSFET disposed in the second transistor region.

### Claim 2 (depends on 1)

The complementary MOSFET of claim 1, wherein the body portion comprises a first material, and the epitaxial portions comprises a second material being different from the first material.

### Claim 3 (depends on 1)

The complementary MOSFET of claim 1, wherein the first vertical interface is a vertical plane.

### Claim 4 (depends on 1)

The complementary MOSFET of claim 1, wherein the gate structure further comprises a gate spacer disposed on sidewalls of the first gate structure.

### Claim 5 (depends on 4)

The complementary MOSFET of claim 4, wherein the gate spacer comprises two opposite surfaces directly in contact with a portion of at least one of the first epitaxial portions.

### Claim 6 (depends on 1)

The complementary MOSFET of claim 1, wherein the substrate comprises a semiconductor substrate and an isolation layer disposed on the semiconductor substrate.

### Claim 7 (depends on 6)

The complementary MOSFET of claim 6, wherein a portion of the semiconductor substrate extrudes through the isolation layer.

### Claim 8 (depends on 7)

The complementary MOSFET of claim 7, further comprising another lightly doped region disposed on an interface between each of the first epitaxial portions and the semiconductor substrate.

### Claim 9 (depends on 1)

The complementary MOSFET of claim 1, wherein the first epitaxial portions comprise epitaxial silicon, epitaxial silicon germanium, epitaxial silicon germanium doped with boron, epitaxial silicon phosphorus, or epitaxial silicon carbon.

### Claim 10 (depends on 1)

A complementary MOSFET of claim 1, wherein the second MOSFET further comprises:
a second fin structure, comprising:
a second body portion; and
two second epitaxial portions respectively disposed on each side of the second body portion, and a second vertical interface is interposed between the second body portion and each of the second epitaxial portions;
two second lightly-doped regions respectively and uniformly formed on each of the entire second vertical interface;
two second doped regions respectively disposed in each of the second epitaxial portions; and
a second gate structure overlying the second body portion.

### Claim 11

A metal oxide semiconductor field-effect transistor (MOSFET) comprising:
a substrate;
a fin structure disposed on the substrate, wherein the fin structure comprises a body portion, two epitaxial portions, and a vertical interface is interposed between the body portion and each of the epitaxial portions;
two lightly-doped regions respectively and uniformly formed on the entire vertical interface;
two doped regions respectively disposed in each of the epitaxial portions; and
a gate structure overlying the body portion of the fin structure.

### Claim 12 (depends on 11)

The MOSFET of claim 11, wherein each of the vertical interfaces is a vertical plane.

### Claim 13 (depends on 11)

The MOSFET of claim 11, further comprising a gate spacer disposed on sidewalls of the gate structure.

### Claim 14 (depends on 13)

The MOSFET of claim 13, wherein the gate spacer comprises two opposite surfaces directly in contact with a portion of at least one of the epitaxial portions.

### Claim 15 (depends on 11)

The MOSFET of claim 11, wherein the substrate comprises a semiconductor substrate and an isolation layer disposed on the semiconductor substrate.

### Claim 16 (depends on 15)

The MOSFET of claim 15, further comprising another lightly-doped region disposed on an interface between each of the epitaxial portions and the semiconductor substrate.

### Claim 17

A method for manufacturing a metal oxide semiconductor field-effect transistor (MOSFET) comprising:
providing a substrate;
forming a fin semiconductor layer on the substrate;
forming a gate electrode overlying a portion of the fin semiconductor layer;
forming a gate spacer disposed on sidewalls of the gate electrode, wherein a portion of the fin semiconductor layer is exposed from the gate spacer;
removing the fin semiconductor layer exposed from the gate spacer so that a vertical interface is exposed from at least one side of the fin semiconductor layer;
forming at least an epitaxial layer on the vertical interface, wherein a lightly-doped region is uniformly formed on the entire vertical interface concurrently during a step for forming the epitaxial layer; and
forming a doped region in the epitaxial layer.

### Claim 18 (depends on 17)

The method of claim 17, wherein the gate spacer is used as an etching mask during a step for removing the fin semiconductor layer exposed from the gate spacer.

### Claim 19 (depends on 17)

The method of claim 17, wherein the vertical interface is a vertical plane.

### Claim 20 (depends on 17)

The method of claim 17, wherein after forming the epitaxial layer, the gate spacer comprises two opposite surfaces directly in contact with a portion of at least one of the epitaxial portions.

### Claim 21 (depends on 17)

The method of claim 17, wherein the substrate comprises a semiconductor substrate and an isolation layer disposed on the semiconductor substrate.

### Claim 22 (depends on 21)

The method of claim 21, wherein a bottom surface of the epitaxial layer is lower than a top surface of the isolation layer.

### Claim 23 (depends on 17)

The method of claim 17, further comprising another lightly-doped region formed on an interface between the epitaxial layer and the semiconductor substrate.