# US 2014/0191316 A1 · Mos transistors and fabrication method thereof

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- Number: US 2014/0191316 A1
- Document ID: US20140191316A1
- Status: Published application
- Kind: A1
- Application number: 13/887,509
- Filed: 2013-05-06
- Published: 2014-07-10
- Earliest claimed: 2013-01-10
- Assignees: Semiconductor Manufacturing International Corp.
- Applicants: Semiconductor Manufacturing International Corp.
- Inventors: NEIL ZHAO
- Web page: https://patentgrep.com/patent/US20140191316A1

## CPC

- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 30/0213: {providing different silicide thicknesses on gate electrodes and on source regions or drain regions}
- H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET}
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 30/6715: {characterised by the doping profiles, e.g. having lightly-doped source or drain extensions}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method is provided for fabricating an MOS transistor. The method includes providing a semiconductor substrate, and forming a gate structure having a gate dielectric layer and a gate metal layer on the semiconductor substrate. The method also includes forming offset sidewall spacers at both sides of the gate structure, and forming lightly doped regions in semiconductor substrate at both sides of the gate structure. Further, the method includes forming a first metal silicide region in each of the lightly doped regions, and forming main sidewall spacers at both sides of the gate structure. Further, the method includes forming heavily doped regions in semiconductor substrate at both sides of the gate structure and the main sidewall spacers, and forming a second metal silicide region in each of the heavily doped regions.

## Claims

### Claim 1

A method for fabricating an MOS transistor, comprising:
providing a semiconductor substrate;
forming a gate structure on the semiconductor substrate;
forming offset sidewall spacers at both sides of the gate structure;
forming lightly doped regions in portions of the semiconductor substrate at both sides of the gate structure and the offset sidewall spacers;
forming a metal silicide region at each of the lightly doped regions;
forming main sidewall spacers on both sides of the off sidewall spacers;
forming heavily doped regions in portions of the semiconductor substrate at both sides of the main sidewall spacers; and
forming a second metal silicide region in each of the heavily doped regions.

### Claim 2 (depends on 1)

The method according to claim 1, wherein:
the semiconductor substrate is a silicon on insulator substrate having a base silicon, a dielectric layer on the base silicon and a top silicon layer on the dielectric layer, and the portions of the semiconductor substrate are in the top silicon layer of the silicon on isolator substrate.

### Claim 3 (depends on 1)

The method according claim 1, wherein:
the first silicide region and the second silicide region are nickel silicide regions or platinum silicide regions.

### Claim 4 (depends on 1)

The method according to claim 1, wherein forming the first silicide region further includes:
forming a first metal layer on a top surface of the semiconductor substrate;
annealing the first metal to react with silicon in the lightly doped region; and
removing unreacted metal of the first metal layer.

### Claim 5 (depends on 1)

The method according to claim 1, wherein forming the second metal silicide region further includes:
forming a second metal layer on one top surface of the semiconductor substrate;
annealing the second metal to react with silicon in the heavily doped region; and
removing unreacted second metal layer.

### Claim 6 (depends on 1)

The method according to claim 1, wherein:
a depth of the lightly doped region is a range of approximately 15 nm˜30 nm; and
a depth of the heavily doped region is a range of approximately 50˜100 nm.

### Claim 7 (depends on 1)

The method according to claim 1, after forming the lightly dope region, further including:
forming halo doped regions by a first low dose halo ion implantation process.

### Claim 8 (depends on 1)

The method according to claim 1, after forming the heavily doped regions, further including:
performing a low temperature diffusion process.

### Claim 9 (depends on 1)

The method according to claim 1, wherein:
a width of the offset sidewall spacers is in a range of approximately 4 nm˜8 nm; and
a width of the main sidewall spacer in in a range of approximately 15 nm˜30 nm.

### Claim 10 (depends on 1)

The method according to claim 1, wherein:
an area of the first metal silicide region is equivalent to an area of the lightly doped region; and
an area of the second metal silicide region is equivalent to an area of the heavily doped region.

### Claim 11 (depends on 1)

The method according to claim 1, after forming the first metal silicide layer, further including:
etching portions of the lightly doped regions at both sides of the gate structure;
forming source drain regions by a selective epitaxial process; and
performing a second halo ion implantation process.

### Claim 12 (depends on 5)

The method according to claim 5, wherein:
the second metal layer is made of nickel or platinum; and
a thickness of the second metal layer is in a range of approximately 30 nm˜100 nm.

### Claim 13 (depends on 1)

The method according to claim 1, wherein:
an annealing temperature for forming the first metal silicide and the second metal silicide is a range of approximately 250° C.˜450° C.

### Claim 14 (depends on 7)

The method according to claim 7, wherein:
an energy of the first halo ion implantation process is in a range of approximately KeV˜60 KeV;
a dose of the first halo ion implantation process is in a range of approximately 1E13 atoms/cm2˜5E13 atoms/cm2; and
an angle of the first halo ion implantation process is in a range of approximately 0°˜40°.

### Claim 15 (depends on 11)

The method according to claim 11, wherein:
a dose of the second halo ion implantation process is in a range of approximately 5E12 atoms/cm2˜2E13 atoms/cm2.

### Claim 16

An MOS transistor, comprising:
a semiconductor substrate;
a gate structure having a gate dielectric layer and a gate electrode on the semiconductor substrate;
offset sidewall spacers and main sidewall spacers on both sides of the gate structure;
source/drain regions formed by lightly doped regions and heavily doped regions;
a first metal silicide region in each of the lightly doped region; and
a second metal silicide region in each of the heavily dope region,
wherein:
the first metal silicide region is formed by: forming a first metal layer on the semiconductor substrate; annealing the first metal layer to react with silicon in the lightly doped region; and removing the unreacted first metal layer; and
the second metal silicide region is formed by: forming a second metal layer on the semiconductor substrate; annealing the second metal layer to react with silicon in the heavily doped region; and removing the unreacted second metal layer.

### Claim 17 (depends on 16)

The MOS transistor according to claim 16, wherein:
the semiconductor substrate is a silicon on insulator substrate; and
the first metal silicide region and the second metal silicide region are nickel silicide regions or platinum silicide regions.

### Claim 18 (depends on 16)

The MOS transistor according to claim 16, wherein:
an area of first metal silicide region is equivalent to an area of the lightly doped region; and
an area of the second metal silicide region is equivalent to an area of the heavily doped region.

### Claim 19 (depends on 16)

The MOS transistor according to claim 16, wherein:
source/drain regions are formed by the lightly doped region and the heavily dope region.

### Claim 20 (depends on 15)

The MOS transistor according to claim 15, wherein:
a total width of the offset sidewall spacers and the main sidewall spacers is greater than a depth of the lightly doped region.