# US 2014/0191315 A1 · Multigate metal oxide semiconductor devices and fabrication methods

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- Number: US 2014/0191315 A1
- Document ID: US20140191315A1
- Status: Published application
- Kind: A1
- Application number: 13/737,682
- Filed: 2013-01-09
- Published: 2014-07-10
- Earliest claimed: 2013-01-09
- Assignees: Broadcom Corporation
- Applicants: Broadcom Corporation
- Inventors: Akira Ito
- Web page: https://patentgrep.com/patent/US20140191315A1

## CPC

- H10D 30/611: {having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733)}
- H10D 30/023: {having multiple independently-addressable gate electrodes influencing the same channel (manufacture or treatment of dual gate TFTs H10D30/031)}
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes a first well and a second well implanted in a semiconductor substrate. The semiconductor device further includes a gate structure above the first and second wells between a raised source structure and a raised drain structure. The raised source structure above is in contact with the first well and connected with the gate structure through a first semiconductor fin structure. The raised drain structure above and in contact with the second well and connected with a second semiconductor fin structure. The second semiconductor fin structure includes at least a gap and a lightly doped portion.

## Claims

### Claim 1

A semiconductor device, comprising:
a first well implanted in a semiconductor substrate;
a second well implanted in the semiconductor substrate;
a gate structure above the first and second wells;
a raised source structure above and in contact with the first well and connected with the gate structure through a first semiconductor fin structure; and
a raised drain structure above and in contact with the second well and connected with a second semiconductor fin structure,
wherein the second semiconductor fin structure comprises a gap separating the gate structure from the raised drain structure.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the first and second semiconductor fin structures have narrower widths than the gate structure.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the first semiconductor fin structure has a narrower width than the raised source structure.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the second semiconductor fin structure has a narrower width than the raised drain structure.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein both the raised source structure and the raised drain structure have narrower widths than the gate structure.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the gate structure comprises a plurality of gates.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the gap has a gap length less than a fin length of the second semiconductor fin structure.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the gap has a non-uniform gap length.

### Claim 9

A semiconductor device, comprising:
a first well having a first well upper surface;
a second well having a second well upper surface;
a gate structure disposed on the first well upper surface and the second well upper surface;
a raised source structure disposed above and in contact with the first well having a source upper surface higher in at least one location than the first well upper surface and connected with the gate structure through a first semiconductor fin structure; and
a raised drain structure disposed on the second well and connected with the gate structure through a second semiconductor fin structure, wherein the second semiconductor fin structure is doped relatively lighter than the first semiconductor fin structure.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the first and second semiconductor fin structures have narrower widths than the gate structure.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the gate structure has a gate upper surface higher than the source and drain upper surfaces.

### Claim 12 (depends on 10)

The semiconductor device of claim 10, wherein the gate structure comprises a plurality of gates.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein the first semiconductor fin structure has a narrower width than the raised source structure.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein the second semiconductor fin structure has a narrower width than the raised drain structure.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein the second semiconductor fin structure comprises a lightly doped portion compared with the first semiconductor fin structure, the lightly doped portion has a length less than a fin length of the second semiconductor fin structure.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein the lightly doped portion has a non-uniform length.

### Claim 17

A method for fabricating a semiconductor device, comprising:
implanting a first well into a semiconductor substrate;
implanting a second well into the semiconductor substrate;
fabricating a first semiconductor fin structure and a second semiconductor fin structure;
fabricating a gate structure partially on the first well and partially on the second well;
fabricating a raised source structure above and in contact with the first well and;
fabricating a raised drain structure above and in contact with the second well and;
wherein:
the first semiconductor fin structure connects the gate structure and the raised source structure;
the second semiconductor fin structure is disposed between the gate structure and the raised drain structure; and
the second semiconductor fin structure comprise at least one of the following:
a gap separating the gate structure from the raised drain structure; and
a lightly doped region that is doped relatively lighter than the first semiconductor fin structure.

### Claim 18 (depends on 17)

The method of claim 17, wherein the first and second semiconductor fin structures have narrower widths than the gate structure.

### Claim 19 (depends on 17)

The method of claim 17, wherein:
the first semiconductor fin structure has a narrower width than the raised source structure; and
the second semiconductor fin structure has a narrower width than the raised drain structure.

### Claim 20 (depends on 19)

The method of claim 19, wherein the second semiconductor fin structure is doped relatively lighter than the first semiconductor fin structure.