# US 2014/0191312 A1 · Semiconductor Device and Method of Forming the Same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2014/0191312 A1
- Document ID: US20140191312A1
- Status: Published application
- Kind: A1
- Application number: 14/140,616
- Filed: 2013-12-26
- Published: 2014-07-10
- Earliest claimed: 2013-01-04
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Yoonhae Kim; Hong Seong Kang; Junjie Xiong; Yoonseok Lee; Youshin Choi
- Web page: https://patentgrep.com/patent/US20140191312A1

## CPC

- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 84/0147: {Manufacturing their gate sidewall spacers}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 64/68: characterised by the insulator, e.g. by the gate insulator
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes a substrate having an active region and a device isolation layer defining the active region, a gate electrode on the active region, source/drain regions at the active region at both sides of the gate electrode, a buffer insulating layer on the device isolation layer, an etch stop layer formed on the buffer insulating layer and extending onto the gate electrode and the source/drain region, a first interlayer insulating layer on the etch stop layer, a first contact and a second contact penetrating the first interlayer insulating layer and the etch stop layer. The first contact and the second contact are spaced apart from each other and are in contact with the source/drain region and the buffer insulating layer, respectively.

## Claims

### Claim 1

A semiconductor device comprising:
a substrate having an active region and a device isolation layer that defines the active region;
a gate electrode on the active region;
a source/drain region at a side of the gate electrode;
a buffer insulating layer on the device isolation layer;
an etch stop layer on the buffer insulating layer and extending onto the gate electrode and the source/drain region;
a first interlayer insulating layer on the etch stop layer; and
a first contact and a second contact each penetrating the first interlayer insulating layer and the etch stop layer, the first contact and the second contact contacting the source/drain region and the buffer insulating layer, respectively, and the first and second contacts spaced apart from each other.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein a top surface of the buffer insulating layer is higher than a top surface of the source/drain region; and
wherein the top surface of the buffer insulating layer is disposed at substantially the same height as a top surface of the gate electrode.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the gate electrode extends onto the device isolation layer; and
wherein the second contact is in contact with a top surface of the gate electrode on the device isolation layer.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein a bottom surface of the second contact is higher than a top surface of the source/drain region.

### Claim 5 (depends on 3)

The semiconductor device of claim 3, wherein the source/drain region includes an elevated portion that extends above the substrate; and
wherein a top surface of the elevated portion is higher than a bottom surface of the gate electrode.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the source/drain region has a protrusion that extends onto the device isolation layer.

### Claim 7 (depends on 3)

The semiconductor device of claim 3, further comprising:
a second interlayer insulating layer on the first interlayer insulating layer; and
a third contact penetrating the second interlayer insulating layer and contacting a top surface of the first contact,
wherein the second contact further penetrates the second interlayer insulating layer; and
wherein the second contact includes the same material as the third contact.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the gate electrode includes a metal nitride layer.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the gate electrode further includes aluminum or tungsten on the metal nitride layer.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, wherein the source/drain region includes a metal silicide layer disposed in an upper portion the source/drain region.

### Claim 11

A semiconductor device, comprising:
a substrate having a device isolation region and an active region;
a gate electrode on the substrate that crosses the active region and that includes a portion that extends onto the device isolation region;
a source/drain region that extends above the substrate on a first side of the gate electrode;
a buffer insulating layer on the device isolation region between the source/drain region and the portion of the gate electrode that extends onto the device isolation region; and
a contact on the portion of the gate electrode that extends onto the device isolation region and on the buffer insulation layer;
wherein a top surface of the buffer insulation layer is higher above the substrate than is a top surface of the source/drain region.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein the source/drain region extends onto the device isolation region.

### Claim 13 (depends on 11)

The semiconductor device of claim 11, further comprising an etch stop layer on the source/drain region and on the buffer insulation layer.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein the contact comprises a first contact, the semiconductor device further comprising:
an interlayer insulating layer on the etch stop layer; and
a second contact,
wherein the first and second contacts each penetrate the interlayer insulating layer and the etch stop layer so that the first contact electrically connects to the gate electrode and the second contact electrically connects to the source/drain region, and
wherein the first contact is spaced apart from the second contact.

### Claim 15 (depends on 11)

The semiconductor device of claim 11, wherein the entirety of the contact is above the buffer insulating layer and the gate electrode.

### Claim 16 (depends on 11)

The semiconductor device of claim 11, wherein the top surface of the buffer insulating layer is substantially coplanar with a top surface of the gate electrode.

### Claim 17 (depends on 11)

The semiconductor device of claim 11, wherein the top surface of the source/drain region is higher above the substrate than is a bottom surface of the gate electrode.

### Claim 18 (depends on 13)

The semiconductor device of claim 13, further comprising a metal silicide region in an upper surface of the source/drain region.

### Claim 19 (depends on 18)

The semiconductor device of claim 18, wherein the etch stop layer is between the metal silicide region in the upper surface of the source/drain region and the gate electrode.

### Claim at position 20

20-24. (canceled)