# US 2014/0191311 A1 · Semiconductor structure and method for manufacturing the same

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- Number: US 2014/0191311 A1
- Document ID: US20140191311A1
- Status: Published application
- Kind: A1
- Application number: 13/878,655
- Filed: 2012-05-18
- Published: 2014-07-10
- Earliest claimed: 2012-05-02
- Assignees: Institute of Microelectronics, Chinese Academy of Sciences
- Inventors: Lijun Dong; Dapeng Chen
- Web page: https://patentgrep.com/patent/US20140191311A1

## CPC

- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/0223: {having source and drain regions or source and drain extensions self-aligned to sides of the gate}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 64/027: {by etching at gate locations}
- H10D 64/0134: {with a treatment, e.g. annealing, after the formation of the insulator and before the formation of the conductor}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 64/665: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum (having lateral variation H10D64/671)}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/668: {the layer being a silicide, e.g. TiSi2}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Provided is a semiconductor structure and a method for manufacturing the same. By the channel reestablishment, the tops of the source/drain regions located on both sides of the spacers are higher than bottoms of the gate stack structure and the spacers, and the source/drain regions laterally extend below the bottoms of the gate stack structure and the spacers and exceed the spacers, thereby reaching the right below of the gate stack structure. Thus, the elevated source/drain MOSFET is obtained. The semiconductor structure reduces the number of process steps, improves efficiency and decreases the cost.

## Claims

### Claim 1

A method for manufacturing a semiconductor structure, comprising the steps of:
a) providing a substrate;
b) forming a dummy gate stack and source/drain regions on the substrate,
wherein the dummy gate stack at least comprises a dummy gate; and the source/drain regions are located on both sides of the dummy gate stack and extend to right below of the dummy gate stack;
c) forming an interlayer dielectric layer that covers the substrate, the source/drain regions and the dummy gate stack;
d) removing a part of the interlayer dielectric layer to expose the dummy gate stack;
e) removing the dummy gate stack and a part of the substrate right below the dummy gate stack, so as to form an opening, right below which parts of the source/drain regions are reserved;
f) forming spacers attached to inner sidewalls of the opening; and
g) forming a gate dielectric layer at a bottom of the opening, and filling a conductive material (260) to form a gate stack structure.

### Claim 2 (depends on 1)

The method according to claim 1, wherein in step b), the source/drain regions extending to the right below of the dummy gate stack are obtained by firstly forming the dummy gate stack, and then performing a source/drain implantation and an annealing.

### Claim 3 (depends on 1)

The method according to claim 1, wherein in step b), the source/drain regions extending to the right below of the dummy gate stack are obtained by firstly forming the source/drain regions, and then forming the dummy gate stack.

### Claim 4 (depends on 1)

The method according to claim 1, wherein in step b), the parts of the source/drain regions extending to the right below of the dummy gate stack have a width of about 10 nm to 20 nm.

### Claim 5 (depends on 1)

The method according to claim 1, wherein in step b), the source/drain regions located on both sides of the dummy gate stack have a depth of about 50 nm to 100 nm.

### Claim 6 (depends on 1)

The method according to claim 1, wherein in step e), a size of the reserved parts of the source/drain regions is controlled by controlling etching time.

### Claim 7 (depends on 1)

The method according to claim 1, wherein in step e), the bottom of the opening is lower than tops of the source/drain regions on both sides for about 10 nm to 50 nm.

### Claim 8 (depends on 1)

The method according to claim 1, wherein in step f), a width of the spacers is not more than that of the parts of the source/drain regions reserved right below the opening.

### Claim 9

A semiconductor structure, comprising:
a substrate;
a gate stack structure partially embedded into the substrate and spacers; and
source/drain regions formed in the substrate, wherein
tops of the source/drain regions located on both sides of the spacers are higher than bottoms of the gate stack structure and the spacers, and
the source/drain regions laterally extend below the bottoms of the gate stack structure and the spacers and exceed the spacers, thereby reaching right below of the gate stack structure.

### Claim 10 (depends on 9)

The structure according to claim 9, wherein the bottom of the gate stack structure is lower than the tops of the source/drain regions on both sides for about 10 nm to 50 nm.

### Claim 11 (depends on 9)

The structure according to claim 9, wherein the source/drain regions located on both sides of the gate stack structure have a depth of about 50 nm to 100 nm.