# US 2014/0191308 A1 · Self-aligned double patterning for memory and other microelectronic devices

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- Number: US 2014/0191308 A1
- Document ID: US20140191308A1
- Status: Published application
- Kind: A1
- Application number: 14/204,373
- Filed: 2014-03-11
- Published: 2014-07-10
- Earliest claimed: 2009-01-28
- Assignees: Spansion LLC
- Applicants: Spansion LLC
- Inventors: Tzu-Yen HSIEH
- Web page: https://patentgrep.com/patent/US20140191308A1

## CPC

- H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- H10B 43/10: characterised by the top-view layout
- H10B 43/30: characterised by the memory core region
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A semiconductor device is provided. The semiconductor device includes a microelectronic layer, a first mask layer formed on the microelectronic layer having first features separated by first openings, and a second mask layer formed on the first mask layer having second features that are separated by second openings. Each second feature is centrally located on a respective one of the first features. A length each second feature in a dimension is substantially equal to a length of a respective one of the first openings in the dimension.

## Claims

### Claim 1

A semiconductor device, comprising:
a microelectronic layer;
a first mask layer formed on the microelectronic layer having first features separated by first openings; and
a second mask layer formed on the first mask layer having second features that are separated by second openings;
wherein each second feature is centrally located on a respective one of the first features and wherein a length of each second feature in a dimension is substantially equal to a length of a respective one of the first openings in the dimension.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the microelectronic layer comprises a layered stack.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the layered stack comprises:
a tunneling layer.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein the layered stack further comprises:
a charge trapping layer that contacts the tunneling layer.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein the layered stack further comprises:
a dielectric layer that contacts the charge trapping layer.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the layered stack further comprises:
a polysilicon layer that contacts the dielectric layer.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, further comprising:
a film that fills the first openings and the second openings.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, further comprising:
a photoresist mask layer that contacts the second mask layer.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the photoresist mask layer includes third features separated by third openings, wherein each third feature contacts a respective one of the second features, and Wherein each third opening coincides with a respective one of the second openings.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, further comprising:
spacers, wherein each spacer contacts a sidewall portion of a respective one of the third features and a sidewall portion of a respective one of the second features.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein a height of each of the spacers relative to the first mask layer is substantially equal to a height of the respective one of the third features relative to the first mask layer.

### Claim 12 (depends on 1)

The semiconductor device of claim 1, wherein the first mask layer comprises a silicon nitride layer.

### Claim 13 (depends on 1)

The semiconductor device of claim 1, wherein the first mask layer comprises a silicon-oxy-nitride layer.

### Claim 14 (depends on 1)

The semiconductor device of claim 1, wherein the semiconductor device comprises a NAND memory.

### Claim 15 (depends on 1)

The semiconductor device of claim 1, wherein the semiconductor device comprises a NOR memory.

### Claim 16 (depends on 1)

The semiconductor device of claim 1, wherein the length of each second feature is substantially equal to one-third of a length of a respective one of the first features.

### Claim 17 (depends on 1)

The semiconductor device of claim 1, wherein the second mask layer comprises a polysilicon material.