# US 2014/0191307 A1 · Memory device and method of fabricating thereof

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- Number: US 2014/0191307 A1
- Document ID: US20140191307A1
- Status: Published application
- Kind: A1
- Application number: 14/207,035
- Filed: 2014-03-12
- Published: 2014-07-10
- Earliest claimed: 2011-09-27
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Giulio Albini; Paola Bacciaglia
- Web page: https://patentgrep.com/patent/US20140191307A1

## CPC

- H10D 64/665: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum (having lateral variation H10D64/671)}
- H10B 43/00: EEPROM devices comprising charge-trapping gate insulators
- H10D 30/694: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 64/037: {comprising charge-trapping insulators}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 30/0413: {of FETs having charge-trapping gate insulators, e.g. MNOS transistors}
- H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- H10D 64/01308: {the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal}
- H10D 64/01324: {characterised by the sectional shape, e.g. T or inverted-T}
- H10D 64/664: {the additional layers comprising a barrier layer between the layer of silicon and an upper metal or metal silicide layer}
- H10D 64/669: {the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

Subject matter disclosed herein relates to a process flow to form a gate structure of a memory device.

## Claims

### Claim 1

A memory device comprising:
a gate stack disposed on a semiconductor substrate, the gate stack including:
a hard mask layer;
a control gate layer; and
a conducting material layer covered by the hard mask layer; and
spacers covering sides of the conducting material layer while exposing sides of the control gate layer, wherein the conducting material layer comprises TaN.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the hard mask layer comprises an oxide.

### Claim 3 (depends on 1)

The memory device of claim 1, wherein the conducting material layer comprises tungsten.

### Claim 4 (depends on 1)

The memory device of claim 1, wherein the spacers comprise nitride.

### Claim 5 (depends on 1)

The memory device of claim 1, further comprising a high voltage (HV) or low voltage (LV) oxide layer disposed between the semiconductor substrate and the control gate layer.

### Claim 6 (depends on 1)

The memory device of claim 1, wherein the control gate layer comprises polysilicon.

### Claim 7 (depends on 6)

The memory device of claim 6, wherein the control gate layer comprises n-doped polysilicon or p-doped polysilicon.

### Claim 8 (depends on 1)

The memory device of claim 1, wherein the conducting material layer comprises at least two distinct material layers having distinct compositions.

### Claim 9 (depends on 8)

The memory device of claim 8, wherein the conducting material layer comprises a first conducting material layer and a second conducting material layer both the first conducting material layer and the second conducting material layer comprising tungsten and TaN, wherein the first conducting material layer comprises a proportion of tungsten to TaN different from that of the second conducting material layer.

### Claim 10

A system comprising:
a transistor of a memory device, the transistor including spacers covering sides of a conducting material layer while exposing sides of a control gate layer in a gate stack, wherein the conducting material layer comprises TaN, and wherein the conducting material layer is covered by a hard mask layer;
a memory controller to control the memory device;
a processing unit to initiate commands to the memory controller for controlling the memory device; and
a bus to connect the memory controller to the processing unit.

### Claim 11 (depends on 10)

The system of claim 10, wherein the hard mask layer comprises at least one of oxide, nitride, and SiON.

### Claim 12 (depends on 10)

The system of claim 10, wherein the conducting material layer further comprises tungsten.

### Claim 13 (depends on 10)

The system of claim 10, wherein the conducting material layer comprises a high-EF material.

### Claim 14 (depends on 10)

The system of claim 10, wherein the control gate layer comprises polysilicon.

### Claim 15 (depends on 10)

The system of claim 10, wherein the spacers further cover sides of the hard mask layer.

### Claim 16 (depends on 10)

The system of claim 10, wherein the conducting material further comprises titanium.

### Claim 17 (depends on 10)

The system of claim 10, wherein the conducting material layer comprises at least two distinct material layers having distinct compositions.

### Claim 18 (depends on 10)

The system of claim 10, wherein the transistor further comprises a gate oxide between the control gate layer and a semiconductor substrate of the transistor.

### Claim 19 (depends on 10)

The system of claim 10, wherein the memory device comprises phase change memory.

### Claim 20 (depends on 10)

The system of claim 10, wherein the memory device comprises flash memory.