# US 2014/0191306 A1 · Semiconductor Constructions, Methods of Forming Vertical Memory Strings, and Methods of Forming Vertically-Stacked Structures

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- Number: US 2014/0191306 A1
- Document ID: US20140191306A1
- Status: Published application
- Kind: A1
- Application number: 13/735,908
- Filed: 2013-01-07
- Published: 2014-07-10
- Earliest claimed: 2013-01-07
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: John D. Hopkins
- Web page: https://patentgrep.com/patent/US20140191306A1

## CPC

- H10D 30/693: {Vertical IGFETs having charge trapping gate insulators}
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10D 30/0411: {of FETs having floating gates}
- H10D 30/0413: {of FETs having charge-trapping gate insulators, e.g. MNOS transistors}
- H10D 30/689: {Vertical floating-gate IGFETs}
- H10D 30/6892: {having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate}
- H10D 30/696: {having at least one additional gate, e.g. program gate, erase gate or select gate}
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10D 64/037: {comprising charge-trapping insulators}
- H10D 64/681: {having a compositional variation, e.g. multilayered}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Some embodiments include methods of forming vertical memory strings. A trench is formed to extend through a stack of alternating electrically conductive levels and electrically insulative levels. An electrically insulative panel is formed within the trench. Some sections of the panel are removed to form openings. Each opening has a first pair of opposing sides along the stack, and has a second pair of opposing sides along remaining sections of the panel. Cavities are formed to extend into the electrically conductive levels along the first pair of opposing sides of the openings. Charge blocking material and charge-storage material is formed within the cavities. Channel material is formed within the openings and is spaced from the charge-storage material by gate dielectric material. Some embodiments include semiconductor constructions, and some embodiments include methods of forming vertically-stacked structures.

## Claims

### Claim 1

A method of forming vertically-stacked structures, comprising:
forming a stack of alternating electrically conductive levels and electrically insulative levels over a base;
forming an electrically insulative panel that extends through the stack; the panel having a pair of opposing sides along the stack;
removing some sections of the panel while leaving other sections remaining; openings being formed where sections of the panel are removed; each opening having a first pair of opposing sides along the stack, and having a second pair of opposing sides along remaining sections of the panel;
forming cavities extending into the electrically conductive levels along the first pair of opposing sides of the openings;
forming dielectric material along exposed edges of the electrically conductive levels within the cavities; and
after forming the dielectric material, forming electrically conductive material within the cavities.

### Claim 2 (depends on 1)

The method of claim 1 wherein a plurality of the electrically insulative panels are formed.

### Claim 3 (depends on 2)

The method of claim 2 wherein the plurality electrically insulative panels are configured as a plurality of substantially parallel panels.

### Claim 4 (depends on 1)

The method of claim 1 wherein the electrically insulative panel is formed to comprise a plurality of linear regions joined to one another through curved regions; wherein the linear regions are substantially parallel to one another; and wherein the openings are formed only within the linear regions.

### Claim 5 (depends on 1)

The method of claim 1 wherein the electrically insulative panel consists of silicon dioxide.

### Claim 6

A method of forming vertical memory strings, comprising:
forming a stack of alternating electrically conductive levels and electrically insulative levels over a base;
forming a trench extending through the stack;
forming an electrically insulative panel within the trench; the panel having a pair of opposing sides along the stack;
removing some sections of the panel while leaving other sections remaining;
openings being formed where sections of the panel are removed; each opening having a first pair of opposing sides along the stack, and having a second pair of opposing sides along remaining sections of the panel;
forming cavities extending into the electrically conductive levels along the first pair of opposing sides of the openings;
forming charge blocking material along exposed edges of the electrically conductive levels within the cavities;
forming charge-storage material within the cavities along the charge blocking material;
forming gate dielectric material along the charge-storage material; and
forming channel material within the openings and spaced from the charge-storage material by the gate dielectric material.

### Claim 7 (depends on 6)

The method of claim 6 wherein a plurality of the trenches are formed, and wherein a plurality of the panels are formed within said plurality of the trenches.

### Claim 8 (depends on 7)

The method of claim 7 wherein the plurality of electrically insulative panels are configured as a plurality of substantially parallel panels.

### Claim 9 (depends on 6)

The method of claim 6 wherein the trench is formed to comprise a plurality of linear regions joined to one another through curved regions; and wherein the electrically insulative panel formed within the trench comprises a plurality of linear regions joined to one another through curved regions; wherein the linear regions of the panel are substantially parallel to one another; and wherein the openings are formed only within the linear regions of the panel.

### Claim 10 (depends on 6)

The method of claim 6 wherein the charge blocking material within each cavity comprises a silicon nitride structure sandwiched between silicon dioxide structures.

### Claim 11 (depends on 10)

The method of claim 10 wherein the silicon nitride structure and the silicon dioxide structures within each cavity are all substantially planar.

### Claim 12 (depends on 11)

The method of claim 11 wherein the silicon nitride structures are formed by:
forming silicon nitride within the cavities, the silicon nitride being along tops and bottoms of the cavities as well as along silicon dioxide structures at the edges of the electrically conductive levels;
forming sacrificial material within the cavities;
removing the silicon nitride from the top and bottom surfaces of the cavities while the sacrificial material protects the silicon nitride along the silicon dioxide structures at the edges of the electrically conductive levels; and
removing the sacrificial material.

### Claim 13 (depends on 6)

The method of claim 6 wherein the electrically conductive levels have a thickness along a cross-section, and wherein the charge-storage material within each cavity has a same thickness along the cross-section as the electrically conductive levels.

### Claim 14

A semiconductor construction, comprising:
a stack of alternating electrically conductive levels and electrically insulative levels over a semiconductor base;
electrically insulative pillars extending through the stack;
channel material posts between the pillars; the channel material posts having a first pair of opposing sides and a second pair of opposing sides; the first pair of opposing sides being spaced from adjacent pillars by intervening regions of the stack; none of the stack is between each of the sides of the second pair of opposing sides and pillars adjacent such sides of the second pair;
cavities extending into the electrically conductive levels along the first pair of opposing sides of the channel material posts;
charge blocking material along edges of the electrically conductive levels within the cavities;
charge-storage material within the cavities and spaced from the electrically conductive levels by the charge blocking material; and
gate dielectric material between the charge-storage material and the channel material posts.

### Claim 15 (depends on 14)

The construction of claim 14 wherein the charge-storage material comprises floating gate material.

### Claim 16 (depends on 14)

The construction of claim 14 wherein the charge-storage material comprises charge-trapping material.

### Claim 17 (depends on 14)

The construction of claim 14 wherein the charge blocking material comprises silicon dioxide.

### Claim 18 (depends on 14)

The construction of claim 14 wherein the charge blocking material within each cavity comprises a silicon nitride structure sandwiched between a pair of silicon dioxide structures.

### Claim 19 (depends on 18)

The construction of claim 18 wherein the silicon nitride structure and the silicon dioxide structures within each cavity are all substantially planar.

### Claim 20 (depends on 14)

The construction of claim 14 wherein the electrically conductive levels comprise conductively doped silicon, and wherein the electrically insulative levels comprise silicon dioxide.

### Claim 21 (depends on 14)

The construction of claim 14 wherein the posts and pillars are part of a serpentining structure that extends through the stack; the electrically conductive levels being incorporated into vertically-stacked control gates; the serpentining structure separating the control gates into a first set on one side of the serpentining structure and a second set on an opposing side of the serpentining structure; all control gates of the first set that are at a common vertical level are electrically coupled to one another, and all control gates of the second set that are at a common vertical level are electrically coupled to one another but not to the control gates of the first set.

### Claim 22 (depends on 21)

The construction of claim 21 wherein the serpentining structure comprises a plurality of linear regions joined to one another through curved regions; wherein the linear regions are substantially parallel to one another; and wherein the channel material posts are only within the linear regions.

### Claim 23 (depends on 22)

The construction of claim 22 wherein the curved regions and the pillars are a same composition as one another.

### Claim 24 (depends on 22)

The construction of claim 22 wherein the curved regions and the pillars both consist of silicon dioxide.

### Claim 25 (depends on 14)

The construction of claim 14 wherein the channel material posts are entirely laterally surrounded by the gate dielectric material.

### Claim 26 (depends on 14)

The construction of claim 14 wherein the channel material posts are spaced from the electrically insulative pillars by only the gate dielectric material along a cross-section.

### Claim 27 (depends on 14)

The construction of claim 14 wherein the channel material posts are directly against the electrically insulative pillars along a cross-section.

### Claim 28 (depends on 14)

The construction of claim 14 wherein the electrically insulative pillars consist of silicon dioxide.