# US 2014/0191305 A1 · Integrated Switch Devices

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- Number: US 2014/0191305 A1
- Document ID: US20140191305A1
- Status: Published application
- Kind: A1
- Application number: 14/205,281
- Filed: 2014-03-11
- Published: 2014-07-10
- Earliest claimed: 2010-08-11
- Assignees: Sarda Technologies, Inc.
- Inventors: James L. Vorhaus
- Web page: https://patentgrep.com/patent/US20140191305A1

## CPC

- H10D 89/811: {using FETs as protective elements}
- H10D 64/257: {for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/512: {Disposition of the gate electrodes, e.g. buried gates}
- H10D 84/01: Manufacture or treatment
- H10D 84/0158: {the components including FinFETs}
- H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Various aspects of the technology include an integrated circuit device comprising a compound semiconductor layer and a plurality of input, switch, and ground ohmic metal fingers fabricated on the compound semiconductor layer in a repeating sequence. A control gate may be disposed between each input finger and adjacent switch finger, and a sync gate may be disposed between each ground finger and adjacent switch finger. A sync gate and a control gate may be disposed adjacent each switch finger. The device further includes a plurality of control gate pads, each control gate pad at an end of two control gates, and a control gate pad at opposite ends of each control gate, and a plurality of sync gate pads, each sync gate pad at an end of two sync gates, and a sync gate pad at opposite ends of each sync gate.

## Claims

### Claim 1

A device comprising:
a compound semiconductor layer;
a plurality of ohmic metal fingers fabricated on the compound semiconductor layer in a repeating pattern including a sequence of:
an input finger,
a switch finger,
a ground finger referenced to a ground,
a switch finger; and
an input finger;
a control gate disposed between each input finger and adjacent switch finger;
a sync gate disposed between each ground finger and adjacent switch finger, a sync gate and a control gate adjacent each switch finger;
a plurality of control gate pads, each control gate pad at an end of two control gates, and a control gate pad at opposite ends of each control gate; and
a plurality of sync gate pads, each sync gate pad at an end of two sync gates, and a sync gate pad at opposite ends of each sync gate.

### Claim 2 (depends on 1)

The device of claim 1, further comprising a control gate pad disposed between a sync gate pad and an input finger.

### Claim 3 (depends on 1)

The device of claim 1, further comprising a sync gate pad disposed between a control gate pad and a ground finger.

### Claim 4 (depends on 1)

The device of claim 1, further comprising a first metallic layer of parallel metal electrodes including:
a plurality of input electrodes, each input electrode electrically coupled to a plurality of input fingers through one or more vias disposed on each of the input fingers;
a plurality of switch electrodes, each switch electrode electrically coupled to a plurality of switch fingers through one or more vias disposed on each of the switch fingers; and
a plurality of ground electrodes, each ground electrode electrically coupled to a plurality of round fingers through one or more vias disposed on each of the ground fingers.

### Claim 5 (depends on 4)

The device of claim 4, wherein the plurality of metal electrodes are arrayed in a repeating pattern including a sequence of:
an input electrode;
a switch electrode;
a ground electrode;
a switch electrode; and
an input electrode.

### Claim 6 (depends on 4)

The device of claim 4, further comprising a second metallic layer for providing electrical communication to the electrodes of the first metallic layer, the second metallic layer comprising:
an input electrode;
a ground electrode;
an output electrode; and
a plurality of gate electrodes.

### Claim 7 (depends on 1)

The device of claim 1, further comprising:
a package substrate, the plurality of ohmic metal fingers fabricated on the compound semiconductor layer embedded in the package substrate;
a decoupling capacitor mounted directly above the compound semiconductor layer embedded in the package substrate; and
an organic layer disposed between the compound semiconductor layer and the decoupling capacitor.

### Claim 8 (depends on 1)

The device of claim 1, further comprising an e-mode FET configured as a normally off component to protect the control FET upon power up of the device, the control FET, sync FET and e-mode FET fabricated on the compound semiconductor layer as a monolithic device.

### Claim 9 (depends on 8)

The device of claim 8, further wherein the e-mode protection FET comprises:
a plurality of first and second e-mode ohmic metal fingers, each of the first e-mode ohmic metal fingers contiguous with a first control ohmic metal finger of the control FET;
an e-mode gate finger disposed between each adjacent first e-mode ohmic metal finger and second e-mode ohmic metal finger; and
for each of the second e-mode ohmic metal fingers, an e-mode gate pad and a control gate pad disposed between the second e-mode ohmic metal fingers and a second control ohmic metal finger, the second control ohmic metal finger aligned with the second e-mode ohmic metal finger, each e-mode gate pad at an end of two e-mode gate fingers.

### Claim 10 (depends on 1)

The device of claim 1, further comprising a sense area fabricated on the compound semiconductor layer, the sense area comprising:
a first sense ohmic metal finger parallel to and aligned with ground finger;
a second sense ohmic metal finger contiguous with the switch finger;
a non-conductive region disposed between the first sense ohmic metal finger and the ground finger; and
a continuous sync gate finger disposed adjacent the first and second sense ohmic metal finger and between the ground finger and switch finger.

### Claim 11

A multiple Field Effect Transistor (FET) device comprising:
a compound semiconductor layer;
a sync FET;
a control FET including a plurality of first control ohmic metal fingers and second control ohmic metal fingers; and
an e-mode FET configured as a normally off component to protect the control FET upon power up of the device, the control FET, sync FET and e-mode FET fabricated on the compound semiconductor layer as a monolithic device.

### Claim 12 (depends on 11)

The device of claim 11, wherein the e-mode protection FET comprises:
a plurality of first and second e-mode ohmic metal fingers, each of the first e-mode ohmic metal fingers contiguous with a first control ohmic metal finger of the control F E T;
an e-mode gate finger disposed between each adjacent first e-mode ohmic metal finger and second e-mode ohmic metal finger; and
for each of the second e-mode ohmic metal fingers, an e-mode gate pad and a control gate pad disposed between the second e-mode ohmic metal fingers and a second control ohmic metal finger, the second control ohmic metal finger aligned with the second e-mode ohmic metal finger, each e-mode gate pad at an end of two e-mode gate fingers.

### Claim 13 (depends on 12)

The device of claim 12, further comprising:
a package substrate, the compound semiconductor layer embedded in the package substrate;
a decoupling capacitor mounted directly above the compound semiconductor layer embedded in the package substrate; and
an organic layer disposed between the die and the decoupling capacitor.

### Claim 14 (depends on 12)

The device of claim 12, further comprising a sense area fabricated on the compound semiconductor layer the sense area comprising:
a first sense ohmic metal finger parallel to and aligned with the first sync ohmic metal finger;
a second sense ohmic metal finger contiguous with the second sync ohmic metal finger;
a non-conductive region disposed between the first sense ohmic metal finger and the first sync ohmic metal finger; and
a continuous sync gate finger disposed adjacent the first and second sense ohmic metal finger and between the first and second sync ohmic metal finger.

### Claim 15 (depends on 14)

The device of claim 14, further comprising:
a package substrate, the compound semiconductor layer embedded in the package substrate;
a decoupling capacitor mounted directly above the compound semiconductor layer embedded in the package substrate; and
an organic layer disposed between the die and the decoupling capacitor.

### Claim 16

A multiple Field Effect Transistor (FET) device comprising:
a compound semiconductor layer;
a sync and control FET fabricated on the compound semiconductor layer, the sync FET including a first and second sync ohmic metal finger; and
a sense area fabricated on the compound semiconductor layer, the sense area comprising:
a first sense ohmic metal finger parallel to and aligned with the first sync ohmic metal finger;
a second sense ohmic metal finger contiguous with the second sync ohmic metal finger;
a non-conductive region disposed between the first sense ohmic metal finger and the first sync ohmic metal finger; and
a continuous sync gate finger disposed adjacent the first and second sense ohmic metal finger and between the first and second sync ohmic metal finger.

### Claim 17 (depends on 16)

The device of claim 16, further comprising:
a package substrate, the compound semiconductor layer embedded in the package substrate;
a decoupling capacitor mounted directly above the compound semiconductor layer embedded in the package substrate; and
an organic layer disposed between the die and the decoupling capacitor.

### Claim 18

A dual Field Effect Transistor (FET) device comprising:
a compound semiconductor layer;
a control FET fabricated on the compound semiconductor layer, the control FET including a source region, a drain region and a gate region, the control FET further comprising:
an ohmic metal control source finger and an ohmic metal control drain finger disposed on a surface of the compound semiconductor layer in electrical contact with the source region and drain region, respectively,
a control gate finger between the control source finger and the control drain finger, and
a first and second control gate pad at opposite ends of the control gate finger and in electrical contact with the control gate finger;
a sync FET fabricated on the compound semiconductor layer with the control FET as a monolithic device, the sync FET including a source region, a drain region and a gate region, the sync FET further comprising:
an ohmic metal sync source finger and an ohmic metal sync drain finger disposed on the surface of the compound semiconductor layer in electrical contact with the source region and drain region, respectively,
a sync gate finger between the sync source finger and the sync drain finger, and
a first and second sync gate pad at opposite ends of the sync gate finger and in electrical contact with the sync gate finger, the first control gate pad and the first sync gate pad disposed between the control drain finger and the sync source finger;
an electrical connection between the control source finger and the sync drain finger; and
a sense region comprising:
an isolated portion of the sync finger;
a non-conductive region of the sync gate finger configured to electrically isolate the isolated portion of the sync finger from the rest of the sync finger; and
a portion of the sync drain finger adjacent the isolated portion of the sync gate finger.

### Claim 19 (depends on 18)

The device of claim 18, further comprising:
a package substrate, the compound semiconductor layer embedded in the package substrate;
a decoupling capacitor mounted directly above the compound semiconductor layer embedded in the package substrate; and
an organic layer disposed between the die and the decoupling capacitor.

### Claim 20 (depends on 18)

The device of claim 18, further comprising an e-mode FET configured as a normally off component to protect the control FET upon power up of the device, the control FET, sync FET and e-mode FET fabricated on the compound semiconductor layer as a monolithic device.