# US 2014/0191304 A1 · Cmos transistors, fin field-effect transistors and fabrication methods thereof

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- Number: US 2014/0191304 A1
- Document ID: US20140191304A1
- Status: Published application
- Kind: A1
- Application number: 13/921,386
- Filed: 2013-06-19
- Published: 2014-07-10
- Earliest claimed: 2013-01-08
- Assignees: Semiconductor Manufacturing International Corp.
- Applicants: Semiconductor Manufacturing International Corp.
- Inventors: DONGJIANG WANG; STEVEN ZHANG
- Web page: https://patentgrep.com/patent/US20140191304A1

## CPC

- H10D 30/0415: {of FETs having ferroelectric gate insulators}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/4735: {having delta-doped or planar-doped donor layers}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method is provided for fabricating a transistor. The method includes providing a semiconductor substrate; and configuring a channel region along a first direction. The method also includes forming trenches at both sides of the channel region along a second direction; and forming a magnetic material layer in each of the trenches. Further, the method includes magnetizing the magnetic material layers to form a magnetic field in the channel region between adjacent magnetic material layers; and forming source/drain regions at both ends of the channel region along the first direction.

## Claims

### Claim 1

A method for fabricating a transistor, comprising:
providing a semiconductor substrate;
configuring a channel region along a first direction;
forming trenches at both sides of the channel region along a second direction;
forming a magnetic material layer in each of the trenches;
magnetizing the magnetic material layer to form a magnetic field between adjacent magnetic material layers in the channel region; and
forming source/drain regions at both ends of the channel region along the first direction.

### Claim 2 (depends on 1)

The method according claim 1, wherein:
the first direction is a direction from a source region to a drain region; and
the second direction is perpendicular to the first direction.

### Claim 3 (depends on 1)

The method according to claim 1, wherein configuring the channel region further includes:
an active region between two trenches along the first direction is a channel for a CMOS transistor; and
a fin structure along the first direction is a channel region for a fin field-effect transistor.

### Claim 4 (depends on 1)

The method according to claim 1, after forming the magnetic material layer, further including:
forming a gate dielectric layer on the channel region; and
forming a gate on the gate dielectric layer.

### Claim 5 (depends on 1)

The method according to claim 1, before forming the trenches, further including:
forming a fin on the semiconductor substrate;
forming a gate dielectric layer on the semiconductor substrate crossing over the fin;
forming a gate on the gate dielectric layer crossing the fin; and
forming an interlayer dielectric layer on the semiconductor substrate.

### Claim 6 (depends on 1)

The method according to claim 1, before forming the magnetic material layer, further including:
forming a liner layer in the trenches to cover inner surfaces of the trenches.

### Claim 7 (depends on 1)

The method according to claim 1, before forming the magnetic material layer, further including:
forming a first dielectric layer in bottom portions of the trenches.

### Claim 8 (depends on 1)

The method according to claim 1, after forming the magnetic material layer, further including:
removing a top portion of the magnetic material layer; and
forming a second dielectric layer on the magnetic material layer.

### Claim 9 (depends on 1)

The method according to claim 1, wherein forming the source/drain regions further includes:
forming sigma-shape trenches in the semiconductor substrate at both ends of the channel region;
filling the sigma-shape trenches with a semiconductor material;
performing an ion implantation process on the semiconductor material to form the source/drain regions.

### Claim 10 (depends on 1)

The method according to claim 1, after forming the source/drain regions, further including:
forming a stress layer on the semiconductor substrate to cover the source/drain regions and a gate region.

### Claim 11 (depends on 1)

The method according to claim 1, wherein:
a thickness of the magnetic material layer is equal to a depth of the channel region; and
the bottom surface of the magnetic material layer levels with the bottom surface of the channel region.

### Claim 12 (depends on 1)

The method according to claim 1, wherein:
the magnetic material layer is formed by a chemical vapor deposition process, a physical vapor deposition process, or a sputtering process.

### Claim 13 (depends on 1)

The method according to claim 1, wherein:
the magnetic material includes one of iron, nickel, cobalt, iron oxide, nickel oxide, or cobalt oxide, etc., or an alloy made of two or more of iron, nickel, and cobalt.

### Claim 14

A CMOS transistor, comprising:
a semiconductor substrate having an active region;
a gate dielectric layer and a gate on the active region;
magnetic material layers at both sides of the active region along a second direction;
source/drain regions at both sides of the active region along a first direction perpendicular to the second direction;
a channel region between the source/drain regions; and
a magnetic field in the channel region along a second direction,
wherein the magnetic field is formed by:
forming isolation trenches in the semiconductor substrate along the second direction;
forming a magnetic material layer in each of the trenches; and
magnetizing the magnetic material layers to form the magnetic field.

### Claim 15 (depends on 14)

The CMOS transistor according to claim 14, wherein:
a liner layer is formed in each of the trenches to cover an inner surface of each of the trenches;
a first dielectric layer is formed in trenches under the magnetic material layer; and
a second dielectric layer is formed on the magnetic material layer.

### Claim 16 (depends on 14)

The CMOS transistor according to claim 14, wherein:
a cross-section of the CMOS transistor along a first direction and a direction vertical to the semiconductor substrate is referred as a plane of a paper;
if the CMOS transistor is an N type transistor, a direction of the magnetic field is perpendicular to the plane of the paper, and into the plane of the paper; and
if the CMOS transistor is a P type transistor, a direction of the magnetic field is perpendicular to the plane of the paper, and out of the plane of the paper.

### Claim 17 (depends on 14)

The CMOS transistor according to claim 14, wherein:
the source/drain regions are sigma shape trenches filled with an ion implanted semiconductor material; and
a stress layer is formed on the semiconductor substrate to cover the source/drain regions and the gate.

### Claim 18

A fin field-effect transistor, comprising:
a semiconductor substrate;
a fin on the semiconductor substrate extending along a first direction;
a gate crossing over the fin on the semiconductor substrate extending along a second direction perpendicular to the first direction;
an interlayer dielectric layer on the semiconductor substrate;
magnetic material layers having a south pole and a north pole in the interlayer dielectric layer at both sides of the fin along a second direction;
source/drain regions at both ends of the fin along the first direction; and
a magnetic field in a channel region along the second direction under the gate,
wherein the magnetic field is formed by:
forming trenches in the interlayer dielectric layer at both sides of the fin along the second direction;
forming a magnetic material layer in each of the trenches; and
magnetizing the magnetic material layer to form a magnetic field between adjacent magnetic material layers in the channel region.

### Claim 19 (depends on 18)

The fin field-effect transistor according to claim 18, wherein:
a cross-section of the field effect transistor vertical to the second direction is referred as a plane of a paper;
if the fin field-effect transistor is an N type transistor, a direction of the magnetic field is perpendicular to the plane of the paper, and into the plane of the paper; and
if the fin field-effect transistor is a P type transistor, a direction of the magnetic field is perpendicular to the plane of the paper, and out of the plane of the paper.

### Claim 20 (depends on 18)

The fin field-effect transistor according to claim 18, wherein:
a dielectric layer is formed on the magnetic material layer.