# US 2014/0191302 A1 · Photonics device and cmos device having a common gate

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- Number: US 2014/0191302 A1
- Document ID: US20140191302A1
- Status: Published application
- Kind: A1
- Application number: 13/736,672
- Filed: 2013-01-08
- Published: 2014-07-10
- Earliest claimed: 2013-01-08
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Solomon Assefa; William M.J. Green; Steven M. Shank; Yurii A. Vlasov
- Web page: https://patentgrep.com/patent/US20140191302A1

## CPC

- H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS}
- H10D 86/01: Manufacture or treatment
- H10F 39/10: Integrated devices
- H10F 71/1212: {consisting of germanium}
- H10D 64/01356: {the insulator being formed after the semiconductor body, the semiconductor being a Group IV material and not being silicon, e.g. Ge, SiGe or SiGeC (H10D64/01364, H10D64/01366 take precedence)}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/40: characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
- H10D 84/80: characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs (H10D84/40 takes precedence)
- Y02E 10/50: Photovoltaic [PV] energy
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- Y02E: REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION

## Abstract

A semiconductor chip having a photonics device and a CMOS device which includes a photonics device portion and a CMOS device portion on a semiconductor chip; a metal or polysilicon gate on the CMOS device portion, the metal or polysilicon gate having a gate extension that extends toward the photonics device portion; a germanium gate on the photonics device portion such that the germanium gate is coplanar with the metal or polysilicon gate, the germanium gate having a gate extension that extends toward the CMOS device portion, the germanium gate extension and metal or polysilicon gate extension joined together to form a common gate; spacers formed on the germanium gate and the metal or polysilicon gate; and nitride encapsulation formed on the germanium gate. A method is also disclosed pertaining to fabricating the semiconductor chip.

## Claims

### Claim 1

A method for forming a photonics device and a CMOS device with a common gate comprising:
defining a photonics device portion and a CMOS device portion on a semiconductor chip where a photonics device and a CMOS device, respectively, are to be fabricated;
forming a metal or polysilicon gate material on the CMOS device portion;
depositing germanium on the photonics device portion and on the metal or polysilicon gate material on the CMOS device portion;
planarizing the germanium to form a coplanar layer of germanium and metal or polysilicon gate material;
etching the germanium to define a gate on the photonics portion and a gate extension that extends towards the CMOS device portion;
etching the metal or polysilicon gate material to define a gate on the CMOS device portion and a gate extension that extends toward the photonics device portion and joins the gate extension from the germanium gate portion wherein the respective joined gate extensions form a common gate between the photonics device portion and CMOS device portion;
forming spacers on the germanium gate and metal or polysilicon gate;
encapsulating the germanium gate with a nitride; and
heating the photonics device portion to cause melting and crystallization of the germanium gate.

### Claim 2 (depends on 1)

The method of claim 1 wherein between the steps of forming a metal or polysilicon gate material and depositing germanium, further comprising:
depositing a nitride layer on the photonics device portion and CMOS device portion;
depositing an oxide on the nitride layer on the photonics device portion and CMOS device portion;
planarizing the oxide so that it is only on the photonics device portion and it is coplanar with the nitride layer on the CMOS device portion;
forming apertures in the oxide on the photonics device portion and CMOS device portion;
etching the nitride layer through the apertures; and
removing the oxide.

### Claim 3 (depends on 1)

The method of claim 1 wherein between the steps of forming a metal or polysilicon gate material and depositing germanium, further comprising the step of forming a bonding layer on a portion of the metal or polysilicon gate material such that the bonding layer promotes the joining of the respective joined gate extensions that form a common gate between the photonics device portion and CMOS device portion.

### Claim 4 (depends on 3)

The method of claim 3 wherein the bonding layer is an oxynitride.

### Claim 5 (depends on 3)

The method of claim 3 wherein the bonding layer has a thickness of about 10 angstroms.

### Claim 6 (depends on 1)

The method of claim 1 where the semiconductor chip comprises a semiconductor on insulator structure.

### Claim 7 (depends on 1)

The method of claim 1 wherein the respective joined gate extensions that form a common gate between the photonics device portion and CMOS device portion are coplanar.

### Claim 8

A method for forming a photonics device and a CMOS device with a common gate comprising:
defining a photonics device portion and a CMOS device portion on a semiconductor chip where a photonics device and a CMOS device, respectively, are to be fabricated;
forming a metal or polysilicon gate material on the CMOS device portion;
depositing germanium on the photonics device portion and on the metal or polysilicon gate material on the CMOS device portion;
planarizing the germanium to form a coplanar layer of germanium and metal or polysilicon gate material;
etching the germanium to define a gate on the photonics portion;
etching the metal or polysilicon gate material to define a gate on the CMOS device portion;
forming spacers on the germanium gate and metal or polysilicon gate;
encapsulating the germanium gate with a nitride; and
heating the photonics device portion to cause melting and crystallization of the germanium gate.

### Claim 9 (depends on 8)

The method of claim 8 wherein the step of etching the germanium further includes etching the germanium to define a gate extension that extends towards the CMOS device portion and wherein the step of etching the metal or polysilicon gate material further includes etching the metal or polysilicon gate material to define a gate extension that extends toward the photonics device portion and joins the gate extension from the germanium gate portion wherein the respective joined gate extensions form a common gate between the photonics device portion and CMOS device portion.

### Claim 10 (depends on 8)

The method of claim 8 wherein between the steps of forming a metal or polysilicon gate material and depositing germanium, further comprising:
depositing a nitride layer on the photonics device portion and CMOS device portion;
depositing an oxide on the nitride layer on the photonics device portion and CMOS device portion;
planarizing the oxide so that it is only on the photonics device portion and it is coplanar with the nitride layer on the CMOS device portion;
forming apertures in the oxide on the photonics device portion and CMOS device portion;
etching the nitride layer through the apertures; and
removing the oxide.

### Claim 11 (depends on 9)

The method of claim 9 wherein between the steps of forming a metal or polysilicon gate material and depositing germanium, further comprising the step of forming a bonding layer on a portion of the metal or polysilicon gate material such that the bonding layer promotes the joining of the respective joined gate extensions that form a common gate between the photonics device portion and CMOS device portion.

### Claim 12 (depends on 11)

The method of claim 11 wherein the bonding layer is an oxynitride.

### Claim 13 (depends on 11)

The method of claim 11 wherein the bonding layer has a thickness of about 10 angstroms.

### Claim 14 (depends on 8)

The method of claim 8 where the semiconductor chip comprises a semiconductor on insulator structure.

### Claim 15 (depends on 9)

The method of claim 9 wherein the respective joined gate extensions that form a common gate between the photonics device portion and CMOS device portion are coplanar.

### Claim at position 16

16-21. (canceled)