# US 2014/0191301 A1 · Transistor and fabrication method

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- Number: US 2014/0191301 A1
- Document ID: US20140191301A1
- Status: Published application
- Kind: A1
- Application number: 14/087,002
- Filed: 2013-11-22
- Published: 2014-07-10
- Earliest claimed: 2013-01-08
- Assignees: Semiconductor Manufacturing International (Shanghai) Corporation
- Applicants: Semiconductor Manufacturing International (Shanghai) Corporation
- Inventors: YOUFENG HE; YONGGEN HE
- Web page: https://patentgrep.com/patent/US20140191301A1

## CPC

- H10D 30/792: {comprising applied insulating layers, e.g. stress liners}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET}
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0147: {Manufacturing their gate sidewall spacers}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0184: {Manufacturing their gate sidewall spacers}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 14/6328: {Deposition from the gas or vapour phase}
- H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD}
- H10P 14/662: {Laminate layers, e.g. stacks of alternating high-k metal oxides (adhesion layers or buffer layers H10P14/6508, H10P14/6548)}
- H10P 14/6682: {the compound being a silane, e.g. disilane, methylsilane or chlorosilane}
- H10P 14/6905: {being a silicon carbide or silicon carbonitride and not containing oxygen, e.g. SiC or SiC:H}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10P 50/283: {by chemical means}
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Transistors and fabrication methods are provided. A first sidewall can be formed on each sidewall of a gate structure. A second sidewall can be formed on the first sidewall. The first sidewall can be made of a doped material. After forming a source and a drain, a metal silicide layer can be formed on the source and the drain. The second sidewall can be removed to expose a surface portion of the semiconductor substrate between the metal silicide layer and the first silicide layer. A stress layer can be formed on the exposed surface portion of the semiconductor substrate, on the metal silicide layer, on the first sidewall, and on the gate.

## Claims

### Claim 1

A method of forming a transistor, comprising:
forming a gate structure on a semiconductor substrate, the gate structure including a gate dielectric layer on the semiconductor substrate and a gate on the gate dielectric layer;
forming a first sidewall on each sidewall of the gate structure, wherein the first sidewall is made of a doped material;
forming a second sidewall on the first sidewall, wherein the second sidewall is formed of a material having an etch rate greater than the first sidewall;
forming a source and a drain in the semiconductor substrate on both sides of the gate structure;
forming a metal silicide layer on the semiconductor substrate associated with each of the source and the drain, such that the second sidewall on the semiconductor substrate is between the metal silicide layer and the first silicide layer;
after forming the metal silicide layer, removing the second sidewall to expose a surface portion of the semiconductor substrate between the metal silicide layer and the first silicide layer; and
forming a stress layer on the surface portion of the semiconductor substrate exposed between the metal silicide layer and the first silicide layer, on the metal silicide layer, on the first sidewall, and on the gate.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first sidewall includes a doping element including carbon or boron, and has a molar concentration of the doping element of about 3% to about 30%.

### Claim 3 (depends on 1)

The method of claim 1, wherein the second sidewall and the first sidewall has an etch selectivity ratio of about 4:1 to about 27:1.

### Claim 4 (depends on 1)

The method of claim 1, wherein the first sidewall has a thickness ranging from about 2 nm to about 10 nm and an etch rate of less than about 5 nm/min in a phosphoric acid solution.

### Claim 5 (depends on 1)

The method of claim 1, wherein forming the first sidewall or the second sidewall includes a chemical vapor deposition or an atomic layer deposition.

### Claim 6 (depends on 1)

The method of claim 1, wherein forming the first sidewall includes using a reaction gas containing SiH2Cl2, NH3, and C2H4 at a reaction temperature ranging from about 450° C. to about 650° C., wherein a SiH2Cl2 flow rate ranges from about 0.1 slm to about 5 slm, a NH3 flow rate ranges from about 0.2 slm to about 5 slm, and a C2H4 flow rate ranges from about 0.1 to 5 slm, and wherein the first sidewall has a carbon concentration ranging from about 1E21 atoms/cm3 to about 5E22 atoms/cm3.

### Claim 7 (depends on 1)

The method of claim 1, wherein the first sidewall includes a multilayer-stacked structure, the multilayer-stacked structure including an un-doped silicon nitride layer and a doped silicon nitride layer stacked together, and wherein the un-doped silicon nitride layer and the doped silicon nitride layer in the first sidewall have a thickness ratio ranging from about 1:2 and 1:50.

### Claim 8 (depends on 7)

The method of claim 7, wherein the undoped silicon nitride layer in the first sidewall is formed by an atomic layer deposition using a reaction gas containing SiH2Cl2 and NH3 at a reaction temperature ranging from about 450° C. to about 650° C. and a reaction pressure ranging from about 0.02 Torr to about 1 Torr, and wherein a SiH2Cl2 flow rate is about 0.2 slm to about 5 slm and a NH3 flow rate is about 0.5 slm to about 10 slm; and wherein the doped silicon nitride layer in the first sidewall is formed by an atomic layer deposition using a reaction gas containing SiH2Cl2, NH3, and C2H4 at a reaction temperature ranging from about 450° C. to about 650° C. and a reaction pressure ranging from about 0.02 Torr to about 1 Torr, wherein a SiH2Cl2 flow rate is about 0.2 slm to about 5 slm, a NH3 flow rate is about 0.5 slm to about 10 slm, and a C2H4 flow rate is about 0.2 slm to about 5 slm.

### Claim 9 (depends on 1)

The method of claim 1, wherein the second sidewall is a silicon nitride layer.

### Claim 10 (depends on 1)

The method of claim 1, wherein the second sidewall includes a multilayer-stacked structure, the multilayer-stacked structure including an un-doped silicon nitride layer and a doped silicon nitride layer stacked together, and wherein the un-doped silicon nitride layer and the doped silicon nitride layer in the second sidewall has a thickness ratio ranging from about 2:1 and 50:1.

### Claim 11 (depends on 10)

The method of claim 10, wherein the doped silicon nitride layer in the second sidewall is doped by a doping element including carbon or boron, and has a molar concentration of the doping element ranging from about 0.5% to about 3%.

### Claim 12 (depends on 10)

The method of claim 10, wherein the multilayer-stacked structure of the second sidewall is formed by a cyclic deposition process.

### Claim 13 (depends on 1)

The method of claim 1, wherein removing the second sidewall includes using a phosphoric acid solution as an etching solution at an etching temperature ranging from about 120° C. to about 165° C. for an etching time ranging from about 1 minute to about 65 minutes.

### Claim 14 (depends on 1)

The method of claim 1, wherein the second sidewall is removed to provide a reduced distance between the stress layer formed on the exposed surface region of the semiconductor substrate and a channel region in the semiconductor substrate under the gate structure.

### Claim 15

A transistor comprising:
a gate structure disposed on a semiconductor substrate, the gate structure including a gate dielectric layer on the semiconductor substrate and a gate on the gate dielectric layer;
a first sidewall disposed on each sidewall of the gate structure, wherein the first sidewall is made of a doped material;
a source and a drain in the semiconductor substrate on both sides of the gate structure;
a metal silicide layer disposed on the semiconductor substrate associated with each of the source and the drain, wherein a surface portion of the semiconductor substrate between the metal silicide layer and the first silicide layer is exposed; and
a stress layer disposed on the surface portion of the semiconductor substrate exposed between the metal silicide layer and the first silicide layer, on the metal silicide layer, on the first sidewall, and on the gate.

### Claim 16 (depends on 15)

The transistor of claim 15, wherein the first sidewall includes a doping element including carbon or boron, and has a molar concentration of the doping element of about 3% to about 30% to provide a reduced dielectric constant.

### Claim 17 (depends on 15)

The transistor of claim 15, wherein the first sidewall has a carbon concentration ranging from about 1E21 atoms/cm3 to about 5E22 atoms/cm3.

### Claim 18 (depends on 15)

The transistor of claim 15, wherein the first sidewall has a thickness ranging from about 2 nm to about 10 nm.

### Claim 19 (depends on 15)

The transistor of claim 15, wherein the first sidewall has an etch rate of less than about 5 nm/min in a phosphoric acid solution.

### Claim 20 (depends on 15)

The transistor of claim 15, wherein the first sidewall includes a multilayer-stacked structure, the multilayer-stacked structure including an un-doped silicon nitride layer and a doped silicon nitride layer stacked together, and wherein the un-doped silicon nitride layer and the doped silicon nitride layer in the first sidewall has a thickness ratio ranging from about 1:2 and 1:50.