# US 2014/0191298 A1 · Semiconductor device and manufacturing method of the same

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- Number: US 2014/0191298 A1
- Document ID: US20140191298A1
- Status: Published application
- Kind: A1
- Application number: 13/737,949
- Filed: 2013-01-10
- Published: 2014-07-10
- Earliest claimed: 2013-01-10
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: Yi-Wei Chen; Chien-Chung Huang; Kok Seen Lew
- Web page: https://patentgrep.com/patent/US20140191298A1

## CPC

- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D 64/01: Manufacture or treatment
- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 64/01125: {the silicides being formed by chemical reaction with the semiconductor after the contact hole formation}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/511: {for IGFETs}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/208: {of electrically inactive species}
- H10W 20/033: {in openings in dielectrics}
- H10W 20/047: {by introducing additional elements therein}
- H10W 20/076: {in via holes or trenches}
- H10D 30/0275: {forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a semiconductor substrate, a metal gate structure, at least an epitaxial layer, an interlayer dielectric, at least a contact hole, at least a metal silicide layer and a fluorine-containing layer. The semiconductor substrate has at least a gate region and at least a source/drain region adjoining the gate region. The gate structure is disposed on the semiconductor substrate within the gate region. The epitaxial layer is disposed on the semiconductor substrate within the source/drain region. The interlayer dielectric covers the semiconductor substrate, the gate structure and the epitaxial layer. The contact hole penetrates the interlayer dielectric to reach the epitaxial layer. The metal silicide layer is formed in the epitaxial layer and is located on the bottom of the contact hole. The fluorine-containing layer is disposed on or in the epitaxial layer and is around sides of the metal silicide layer.

## Claims

### Claim 1

A semiconductor device, comprising:
a semiconductor substrate having at least a gate region and at least a source/drain region adjoining the gate region;
a gate structure disposed on the semiconductor substrate within the gate region;
at least an epitaxial layer disposed on the semiconductor substrate within the source/drain region;
an interlayer dielectric covering the semiconductor substrate, the gate structure and the epitaxial layer;
at least a contact hole penetrating the interlayer dielectric to reach the epitaxial layer;
at least a metal silicide layer formed in the epitaxial layer on a bottom of the contact hole; and
a fluorine-containing layer disposed on or in the epitaxial layer and disposed on a periphery of the metal silicide layer.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the gate structure is a metal gate structure.

### Claim 3 (depends on 2)

The semiconductor device according to claim 2, wherein the metal gate structure further comprises a metal gate and at least a spacer disposed on a sidewall of the metal gate.

### Claim 4 (depends on 3)

The semiconductor device according to claim 3, wherein the spacer has a single-layered structure or a multi-layered structure.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein the fluorine-containing layer is further located under a bottom of the metal silicide layer.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, wherein a position of the fluorine-containing layer disposed on the periphery of the metal silicide layer is higher than a position of the fluorine-containing layer located under a bottom of the metal silicide layer.

### Claim 7 (depends on 1)

The semiconductor device according to claim 1, wherein the epitaxial layer comprises silicon germanium, silicon phosphorous, silicon carbon or phosphorus-doped silicon carbon.

### Claim 8 (depends on 1)

The semiconductor device according to claim 1, wherein the metal silicide layer comprises nickel silicide, nickel platinum silicide, platinum silicide, cobalt silicide or tungsten silicide.

### Claim 9 (depends on 1)

The semiconductor device according to claim 1, wherein the contact hole has an elliptical shape, a bar shape or a circular shape.

### Claim 10 (depends on 1)

The semiconductor device according to claim 1, wherein the semiconductor device is a fin field effect transistor (Fin-FET).

### Claim 11 (depends on 1)

The semiconductor device according to claim 1, wherein the fluorine-containing layer is around sides of the metal silicide layer.

### Claim 12

A method for manufacturing a semiconductor device, comprising:
providing a semiconductor substrate having at least a gate region and at least a source/drain region adjoining the gate region;
forming at least an epitaxial layer on the semiconductor substrate within the source/drain region;
forming a fluorine-containing layer on a surface of the epitaxial layer;
after forming the fluorine-containing layer, forming a metal gate structure within the gate region;
forming an interlayer dielectric covering the semiconductor substrate, the epitaxial layer and the metal gate structure;
forming at least a contact hole penetrating the interlayer dielectric to expose a portion of the epitaxial layer; and
forming at least a metal silicide layer on or in the epitaxial layer on a bottom of the contact hole, wherein the fluorine-containing layer is disposed on a periphery of the metal silicide layer after forming the metal silicide layer.

### Claim 13 (depends on 12)

The method according to claim 12, wherein a process for forming a fluorine-containing layer comprises a fluorine ion implantation process.

### Claim 14 (depends on 12)

The method according to claim 12, wherein a process for forming the fluorine-containing layer comprises:
forming an oxide film conformally covering the epitaxial layer; and
performing an etching process to remove the oxide film, wherein an etchant of the etching process comprises a fluorine-containing molecule.

### Claim 15 (depends on 14)

The method according to claim 14, wherein the oxide film is removed completely or partially through the etching process.

### Claim 16 (depends on 12)

The method according to claim 12, wherein the fluorine-containing layer is further located under a bottom of the metal silicide layer.

### Claim 17 (depends on 12)

The method according to claim 12, wherein a position of the fluorine-containing layer disposed on the periphery of the metal silicide layer is higher than a position of the fluorine-containing layer located under a bottom of the metal silicide layer.

### Claim 18 (depends on 12)

The method according to claim 12, wherein the metal gate structure further comprises a metal gate and at least a spacer disposed on a sidewall of the metal gate.

### Claim 19 (depends on 18)

The method according to claim 18, wherein the spacer has a single-layered structure or a multi-layered structure.

### Claim 20 (depends on 12)

The method according to claim 12, wherein the epitaxial layer comprises silicon germanium, silicon phosphorous, silicon carbon or phosphorus-doped silicon carbon.

### Claim 21 (depends on 12)

The method according to claim 12, wherein the metal silicide layer comprises nickel silicide, nickel platinum silicide, platinum silicide, cobalt silicide or tungsten silicide.

### Claim 22 (depends on 12)

The method according to claim 12, wherein the contact hole has an elliptical shape, a bar shape or a circular shape.

### Claim 23 (depends on 12)

The method according to claim 12, wherein the semiconductor device is a fin field effect transistor.

### Claim 24 (depends on 12)

The method according to claim 12, wherein the fluorine-containing layer is around sides of the metal silicide layer.