# US 2014/0191297 A1 · Strained finfet with an electrically isolated channel > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0191297 A1 - Document ID: US20140191297A1 - Status: Published application - Kind: A1 - Application number: 13/737,089 - Filed: 2013-01-09 - Published: 2014-07-10 - Earliest claimed: 2013-01-09 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporaton - Inventors: Henry K. Utomo; Kangguo Cheng; Ramachandra Divakaruni; Dechao Guo; Myung-Hee Na; Ravikumar Ramachandran; Kern Rim; Huiling Shang - Web page: https://patentgrep.com/patent/US20140191297A1 ## CPC - H10D 30/6215: {having multiple independently-addressable gate electrodes} - H10D 30/024: {of fin field-effect transistors [FinFET]} - H10D 30/62: Fin field-effect transistors [FinFET] - H10D 30/751: {having composition variations in the channel regions} - H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain} - H10D 30/798: {being provided in or under the channel regions} - H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)} - H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes} - H10D 84/0158: {the components including FinFETs} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A fin structure includes an optional doped well, a disposable single crystalline semiconductor material portion, and a top semiconductor portion formed on a substrate. A disposable gate structure straddling the fin structure is formed, and end portions of the fin structure are removed to form end cavities. Doped semiconductor material portions are formed on sides of a stack of the disposable single crystalline semiconductor material portion and a channel region including the top semiconductor portion. The disposable single crystalline semiconductor material portion may be replaced with a dielectric material portion after removal of the disposable gate structure or after formation of the stack. The gate cavity is filled with a gate dielectric and a gate electrode. The channel region is stressed by the doped semiconductor material portions, and is electrically isolated from the substrate by the dielectric material portion. ## Claims ### Claim 1 A semiconductor structure comprising: a vertical stack of a single crystalline semiconductor material portion, a dielectric material portion, and a single crystalline channel portion; a first doped semiconductor material portion epitaxially aligned to said single crystalline semiconductor material portion and said single crystalline channel portion; a second doped semiconductor material portion epitaxially aligned to said single crystalline semiconductor material portion and said single crystalline channel portion and laterally spaced from said first doped semiconductor material portion by said dielectric material portion and said single crystalline channel portion; and a gate stack including a gate dielectric and a gate electrode, said gate stack straddling said dielectric material portion and said single crystalline channel portion. ### Claim 2 (depends on 1) The semiconductor structure of claim 1, wherein said dielectric material portion and said single crystalline channel portion have a same width throughout. ### Claim 3 (depends on 2) The semiconductor structure of claim 2, wherein said single crystalline semiconductor material portion has said same width throughout. ### Claim 4 (depends on 3) The semiconductor structure of claim 3, further comprising a shallow trench isolation structure laterally surrounding said single crystalline semiconductor material portion. ### Claim 5 (depends on 4) The semiconductor structure of claim 4, wherein said vertical stack further comprises a semiconductor material layer, and an upper portion of said semiconductor substrate layer has said same width throughout and contacts said shallow trench isolation structure. ### Claim 6 (depends on 3) The semiconductor structure of claim 3, wherein said single crystalline semiconductor material portion comprises a center portion having a first height, and two end portions have a second height, wherein said first height is greater than said second height. ### Claim 7 (depends on 1) The semiconductor structure of claim 1, wherein first sidewalls of said single crystalline semiconductor material portion, said dielectric material portion, and said single crystalline channel portion in contact with said first doped semiconductor material portion are vertically coincident among one another, and second sidewalls of said single crystalline semiconductor material portion, said dielectric material portion, and said single crystalline channel portion in contact with said second doped semiconductor material portion are vertically coincident among one another. ### Claim 8 (depends on 7) The semiconductor structure of claim 7, further comprising a gate spacer laterally surrounding said gate stack, wherein said first sidewalls and said second sidewalls are vertically coincident with bottom portions of outer sidewalls of said gate spacer. ### Claim 9 (depends on 1) The semiconductor structure of claim 1, further comprising a shallow trench isolation structure laterally contacting, and surrounding, all sidewalls of said single crystalline semiconductor material portion. ### Claim 10 (depends on 9) The semiconductor structure of claim 9, wherein a horizontal interface between said shallow trench isolation structure and said gate stack is located between a horizontal plane including a top surface of said dielectric material portion and a horizontal plane including a bottom surface of said dielectric material portion. ### Claim 11 (depends on 9) The semiconductor structure of claim 9, wherein a first top surface of said shallow trench isolation structure is in contact with a surface of said first doped semiconductor material portion, and a second top surface of said shallow trench isolation structure is in contact with a surface of said second doped semiconductor material portion. ### Claim 12 (depends on 1) The semiconductor structure of claim 1, wherein said gate dielectric is in contact with sidewalls of said dielectric material portion. ### Claim 13 (depends on 1) The semiconductor structure of claim 1, wherein said single crystalline channel portion and said dielectric material portion have a same horizontal cross-sectional shape. ### Claim 14 (depends on 1) The semiconductor structure of claim 1, wherein each of said first and second doped semiconductor material portions includes a lower portion having a same width as said single crystalline semiconductor material portion, said dielectric material portion, and said single crystalline channel portion, and an upper portion having a greater width than said single crystalline semiconductor material portion, said dielectric material portion, and said single crystalline channel portion. ### Claim 15 (depends on 1) The semiconductor structure of claim 1, wherein said first and second doped semiconductor material portions include a semiconductor material having a lattice mismatch with respect to a semiconductor material of said single crystalline semiconductor material portion. ### Claim 16 A method of forming a semiconductor structure comprising: forming a fin structure including a vertical stack of an upper portion of a semiconductor material layer, a single crystalline semiconductor material portion, a disposable single crystalline semiconductor material portion, and a top semiconductor portion; replacing end portions of said fin structure with doped semiconductor material portions that are epitaxially aligned to said single crystalline semiconductor material portion and said single crystalline channel portion; replacing a remainder of said disposable single crystalline semiconductor material portion with a dielectric material portion; and forming a gate structure straddling said single crystalline channel portion and said dielectric material portion, said gate structure including a gate dielectric and a gate electrode. ### Claim 17 (depends on 16) The method of claim 16, further comprising: forming a disposable gate structure straddling said fin structure; forming a gate spacer laterally surrounding said disposable gate structure; and anisotropically etching said end portions of said fin structure in areas that are not covered by said gate spacer or said disposable gate structure. ### Claim 18 (depends on 17) The method of claim 17, wherein horizontal surfaces of said single crystalline semiconductor material portion are physically exposed by said anisotropically etching of said end portions of said fin structure. ### Claim 19 (depends on 18) The method of claim 18, wherein said replacing of end portions of said fin structure with doped semiconductor material portions comprises: forming a first doped semiconductor material portion in epitaxial alignment with said single crystalline semiconductor material portion and said single crystalline channel portion directly on said remainder of said disposable single crystalline semiconductor material portion; and forming a second doped semiconductor material portion in epitaxial alignment with said single crystalline semiconductor material portion and said single crystalline channel portion directly on said remainder of said disposable single crystalline semiconductor material portion. ### Claim 20 (depends on 19) The method of claim 19, wherein said replacing of said remainder of said disposable single crystalline semiconductor material portion with said dielectric material portion comprises: removing said disposable gate structure; removing said remainder of said disposable single crystalline semiconductor material portion; and forming said dielectric material portion above a remainder of single crystalline semiconductor material portion and below a remainder of said top semiconductor portion. ### Claim 21 (depends on 18) The method of claim 18, wherein said replacing of said remainder of said disposable single crystalline semiconductor material portion with said dielectric material portion comprises: removing said remainder of said disposable single crystalline semiconductor material portion after said horizontal surfaces of single crystalline semiconductor material portion are physically exposed and while said disposable gate structure is present; and forming said dielectric material portion above a remainder of single crystalline semiconductor material portion and below a remainder of said top semiconductor portion. ### Claim 22 (depends on 21) The method of claim 21, wherein said replacing of end portions of said fin structure with doped semiconductor material portions comprises: forming a first doped semiconductor material portion in epitaxial alignment with said single crystalline semiconductor material portion and said single crystalline channel portion directly on said dielectric material portion; and forming a second doped semiconductor material portion in epitaxial alignment with said single crystalline semiconductor material portion and said single crystalline channel portion directly on said dielectric material portion. ### Claim 23 (depends on 16) The method of claim 16, wherein said disposable single crystalline semiconductor material portion comprises an n-doped single crystalline silicon, and said method further comprises removing said n-doped single crystalline silicon selective to semiconductor materials of said single crystalline semiconductor material portion and said top semiconductor portion. ### Claim 24 (depends on 16) The method of claim 16, wherein said disposable single crystalline semiconductor material portion comprises porous single crystalline silicon, and said method further comprises removing said porous single crystalline silicon selective to semiconductor materials of said single crystalline semiconductor material portion and said top semiconductor portion. ### Claim 25 (depends on 16) The method of claim 16, wherein said disposable single crystalline semiconductor material portion comprises a silicon-germanium alloy, and said method further comprises removing said silicon germanium alloy selective to semiconductor materials of said single crystalline semiconductor material portion and said top semiconductor portion.