# US 2014/0191296 A1 · Self-aligned dielectric isolation for finfet devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0191296 A1 - Document ID: US20140191296A1 - Status: Published application - Kind: A1 - Application number: 13/735,315 - Filed: 2013-01-07 - Published: 2014-07-10 - Earliest claimed: 2013-01-07 - Assignees: Globalfoundries Inc.; International Business Machines Corporation - Applicants: International Business Machines Corporation; Globalfoundries, Inc. - Inventors: Marc Adam Bergendahl; Kangguo Cheng; David Vaclav Horak; Ali Khakifirooz; Shom Ponoth; Theodorus Eduardus Standaert; Chih-Chao Yang; Charles William Koburger, III; Xiuyu Cai; Ruilong Xie - Web page: https://patentgrep.com/patent/US20140191296A1 ## CPC - H10D 84/834: {comprising FinFETs} - H10D 30/0243: {using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability} - H10D 30/6215: {having multiple independently-addressable gate electrodes} - H10D 30/6217: {having non-uniform gate electrodes, e.g. gate conductors having varying doping} - H10D 62/115: {Dielectric isolations, e.g. air gaps} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract Embodiments of the present invention provide a method of forming semiconductor structure. The method includes forming a set of device features on top of a substrate; forming a first dielectric layer directly on top of the set of device features and on top of the substrate, thereby creating a height profile of the first dielectric layer measured from a top surface of the substrate, the height profile being associated with a pattern of an insulating structure that fully surrounds the set of device features; and forming a second dielectric layer in areas that are defined by the pattern to create the insulating structure. A structure formed by the method is also disclosed. ## Claims ### Claim 1 A method comprising: forming a set of device features on top of a substrate; forming a first dielectric layer directly on top of said set of device features and on top of said substrate, thereby creating a height profile of said first dielectric layer measured from a top surface of said substrate, said height profile being associated with a pattern of an insulating structure that fully surrounds said set of device features; and forming a second dielectric layer in areas that are defined by said pattern to create said insulating structure. ### Claim 2 (depends on 1) The method of claim 1, further comprising, before forming said second dielectric layer, removing a portion of said first dielectric layer to form sidewall spacers next to sidewalls of at least some of said set of device features and to expose portions of said substrate that are defined by said pattern of said insulating structure. ### Claim 3 (depends on 1) The method of claim 1, wherein said set of device features includes at least a first group of device features and a second group of device features, and wherein forming said first dielectric layer comprises causing said first dielectric layer to create said pattern of said insulating structure by said height profile, said pattern of said insulating structure separating said first group of device features from said second group of device features in two enclosures. ### Claim 4 (depends on 3) The method of claim 3, wherein forming said first dielectric layer comprises depositing a conformal dielectric layer on top of said first group and said second group of device features and on top of said substrate, said conformal dielectric layer having a thickness that is sufficiently thick to fill up any gap between any two neighboring said device features either within said first group or within said second group. ### Claim 5 (depends on 3) The method of claim 3, wherein forming said first dielectric layer comprises depositing a conformal dielectric layer as said first dielectric layer, whose thickness is less than half of a shortest distance between said first and said second groups of device features, creating said height profile that complements a height profile of said insulating structure. ### Claim 6 (depends on 3) The method of claim 3, further comprising, before forming said second dielectric layer, directionally etching said first dielectric layer to remove portions of said first dielectric layer that surround said first and second groups of device features to expose said substrate underneath thereof, said directional etching substantially maintains said pattern of said insulating structure. ### Claim 7 (depends on 6) The method of claim 6, further comprising, after forming said second dielectric layer in areas defined by said pattern directly on top of said exposed substrate, removing portions of said second dielectric layer that are deposited on top of said first dielectric layer and on top of said first and second groups of device features. ### Claim 8 (depends on 1) The method of claim 1, wherein said set of device features is a set of fins of a set of fin-type field-effect-transistors (FinFETs), further comprising forming a set of gates for said set of FinFETs substantially perpendicular to and across said set of fins, said set of gates having their respective two ends directly on top of said insulating structure. ### Claim 9 (depends on 8) The method of claim 8, further comprising epitaxially forming source and drain of said set of FinFETs from portions of said substrate adjacent to said set of fins. ### Claim 10 A method comprising: forming a set of fin structures on top of a substrate, said set of fin structures being part of one or more fin-type field-effect-transistors (FinFETs); forming a first dielectric layer directly on top of said set of fin structures and on top of said substrate, said first dielectric layer having a height profile that is complement to a pattern of an insulating structure fully surrounding said set of fin structures; and forming a second dielectric layer in areas defined by said pattern to create said insulating structure. ### Claim 11 (depends on 10) The method of claim 10, wherein said set of fin structures includes at least a first group of fin structures and a second group of fin structures, and wherein forming said first dielectric layer comprises causing said first dielectric layer to create said pattern of said insulating structure by said height profile, said pattern of said insulating structure separating said first group of fin structures from said second groups of fin structures. ### Claim 12 (depends on 11) The method of claim 11, wherein forming said first dielectric layer comprises depositing a conformal dielectric layer to have a thickness, said thickness being more than half of a greatest distance between any two neighboring said fin structures either within said first group or within said second group and being less than half of a shortest distance between said first group of fin structures and said second group of fin structures, creating said height profile that complements a height profile of said insulating structure. ### Claim 13 (depends on 11) The method of claim 11, further comprising, before forming said second dielectric layer, directionally etching said first dielectric layer to remove portions of said first dielectric layer that surround said first and second groups of fin structures to expose said substrate underneath thereof, said directional etching substantially maintaining said pattern of said insulating structure. ### Claim 14 (depends on 13) The method of claim 13, further comprising, after forming said second dielectric layer in areas of said pattern directly on top of said exposed substrate, removing portions of said second dielectric layer that are deposited on top of said first dielectric layer and on top of said first and second groups of fin structures. ### Claim 15 (depends on 10) The method of claim 10, further comprising forming a set of gates of said one or more FinFETs perpendicularly across said set of fin structures, having two ends of said set of gates landing directly on top of said insulating structure. ### Claim 16 (depends on 15) The method of claim 15, further comprising epitaxially forming source and drain of said one or more FinFETs from portions of said substrate adjacent to said set of fin structures. ### Claim 17 A semiconductor structure, comprising: a dielectric structure surrounding a group of fin structures, said dielectric structure having a height that is at least as high as that of said group of fin structures, wherein said group of fin structures are part of one or more fin-type field-effect-transistors (FinFETs). ### Claim 18 (depends on 17) The semiconductor structure of claim 17, wherein said group of fin structures is a first group of fin structures, further comprising a second group of fin structures in parallel with said first group of fin structures and being separated by said dielectric structure, a distance from said dielectric structure to a closest fin structure of said first group is same as a distance from said dielectric structure to a closest fin structure of said second group. ### Claim 19 (depends on 18) The semiconductor structure of claim 18, further comprising at least one gate structure being formed substantially perpendicular to said first group of fin structures with two ends of said at least one gate structure being directly on top of said dielectric structure. ### Claim 20 (depends on 19) The semiconductor structure of claim 19, wherein sources and drains of said one or more FinFETs are epitaxially grown to be constrained by sidewalls of said dielectric structure.