# US 2014/0191295 A1 · Dummy gate interconnect for semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0191295 A1 - Document ID: US20140191295A1 - Status: Published application - Kind: A1 - Application number: 13/734,012 - Filed: 2013-01-04 - Published: 2014-07-10 - Earliest claimed: 2013-01-04 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Brian J. Greene; Yue Liang; Xiaojun Yu - Web page: https://patentgrep.com/patent/US20140191295A1 ## CPC - H10D 64/011: {of electrodes ohmically coupled to a semiconductor} - H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) - H10D 64/01326: {Aspects related to lithography, isolation or planarisation of the conductor} - H10D 89/10: Integrated device layouts - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A method of forming a semiconductor device comprising a dummy gate interconnect includes forming a dummy gate on a substrate, the dummy gate comprising a dummy gate metal layer located on the substrate, and a dummy gate polysilicon layer located on the dummy gate metal layer; forming an active gate on the substrate, the active gate comprising an active gate metal layer located on the substrate, and an active gate polysilicon layer located on the active gate metal layer; and etching the dummy gate polysilicon layer to remove at least a portion of the dummy gate polysilicon layer to form the dummy gate interconnect, wherein the active gate polysilicon layer is not etched during the etching of the dummy gate polysilicon layer. ## Claims ### Claim 1 A method of forming a semiconductor device comprising a dummy gate interconnect, comprising: forming a dummy gate on a substrate, the dummy gate comprising a dummy gate metal layer located on the substrate, and a dummy gate polysilicon layer located on the dummy gate metal layer; forming an active gate on the substrate, the active gate comprising an active gate metal layer located on the substrate, and an active gate polysilicon layer located on the active gate metal layer; and etching the dummy gate polysilicon layer to remove at least a portion of the dummy gate polysilicon layer to form the dummy gate interconnect, wherein the active gate polysilicon layer is not etched during the etching of the dummy gate polysilicon layer. ### Claim 2 (depends on 1) The method of claim 1, wherein forming the dummy gate on the substrate further comprises forming a dummy gate cap on top of the dummy gate polysilicon layer; and wherein forming the active gate on the substrate further comprises forming an active gate cap on top of the active gate polysilicon layer. ### Claim 3 (depends on 2) The method of claim 2, wherein the dummy gate cap and the active gate cap each comprise nitride. ### Claim 4 (depends on 2) The method of claim 2, further comprising removing the dummy gate cap from the dummy gate before etching the dummy gate polysilicon layer, and wherein the active gate cap protects the active gate polysilicon layer during the etching of the dummy gate polysilicon layer. ### Claim 5 (depends on 4) The method of claim 4, further comprising forming a protective layer over the substrate before etching the dummy gate polysilicon layer, wherein the active gate cap and the dummy gate polysilicon layer are not covered by the protective layer, and wherein the protective layer protects the substrate during the etching of the dummy gate polysilicon layer. ### Claim 6 (depends on 5) The method of claim 5, wherein the protective layer comprises one of a polymer material, oxide, and glass. ### Claim 7 (depends on 5) The method of claim 5, wherein forming the protective layer comprises: forming an initial layer of a protective layer material over the semiconductor device; and etching the initial layer to form the protective layer, such that the active gate cap and the dummy gate polysilicon layer are exposed by etching of the initial layer to form the protective layer. ### Claim 8 (depends on 5) The method of claim 5, wherein forming the protective layer comprises: spin-coating a protective layer material on the substrate to form the protective layer, wherein the protective layer has a thickness that is less than a height of the active gate cap and the dummy gate polysilicon layer. ### Claim 9 (depends on 5) The method of claim 5, further comprising: removing the active gate cap after etching the dummy gate polysilicon layer; siliciding a portion of the active gate polysilicon layer to form an active gate silicide; and siliciding a remaining portion of the dummy gate polysilicon layer to form a conductor silicide simultaneously with forming the active gate silicide, wherein the remaining portion of the dummy gate polysilicon layer is fully consumed by the siliciding such that the conductor silicide is in direct contact with the dummy gate metal layer. ### Claim 10 (depends on 9) The method of claim 9, further comprising: removing the protective layer before forming the active gate silicide; and forming source/drain silicide in source/drain regions located on either side of the active gate in the substrate simultaneously with forming the active gate silicide. ### Claim 11 (depends on 2) The method of claim 2, further comprising, before etching the dummy gate polysilicon layer: removing the active gate cap; siliciding a portion of the active gate polysilicon layer to form an active gate silicide; forming source/drain silicide in source/drain regions located on either side of the active gate in the substrate simultaneously with forming the active gate silicide; forming a protective layer over the substrate, wherein the active gate silicide and the dummy gate cap are not covered by the protective layer; forming a mask over the active gate silicide after forming the protective layer; and removing the dummy gate cap; wherein the active gate silicide is protected by the mask and the substrate is protected by the protective layer during the etching of the dummy gate polysilicon layer. ### Claim 12 (depends on 1) The method of claim 1, further comprising: forming a protective layer over the semiconductor device before etching the dummy gate polysilicon layer, wherein the protective layer covers the active gate and the dummy gate, and wherein the protective layer comprises a conformal etch stop material comprising one of oxide and nitride; removing the protective layer from the dummy gate; and etching the dummy gate polysilicon layer, wherein the protective layer protects the active gate polysilicon layer and the substrate during the etching of the dummy gate polysilicon layer. ### Claim 13 (depends on 12) The method of claim 12, further comprising: removing the protective layer from the semiconductor device after etching the dummy gate polysilicon layer; siliciding a portion of the active gate polysilicon layer to form an active gate silicide; siliciding a remaining portion of the dummy gate polysilicon layer to form a conductor silicide simultaneously with forming the active gate silicide, wherein the remaining portion of the dummy gate polysilicon layer is fully consumed by the siliciding such that the conductor silicide is in direct contact with the dummy gate metal layer; and forming source/drain silicide in source/drain regions located on either side of the active gate in the substrate simultaneously with forming the active gate silicide. ### Claim 14 (depends on 1) The method of claim 1, wherein the active gate polysilicon layer and the dummy gate polysilicon layer each further comprise respective etch stop layers comprising titanium nitride (TiN), and wherein the portion of dummy gate polysilicon layer that is removed by the etching of the dummy gate polysilicon layer is determined by a location of the respective etch stop layer in the dummy gate polysilicon layer. ### Claim 15 (depends on 1) The method of claim 1, wherein the portion of dummy gate polysilicon layer that is removed by the etching of the dummy gate polysilicon layer is determined by an etch time of the etching of the dummy gate polysilicon layer. ### Claim 16 (depends on 1) The method of claim 1, wherein all of the dummy gate polysilicon layer by the etching of the dummy gate polysilicon layer. ### Claim 17 A semiconductor device comprising, comprising: an active gate, the active gate comprising an active gate stack comprising an active gate metal layer located on a substrate and an active gate polysilicon layer located on top of the active gate metal layer; and a dummy gate interconnect, the dummy gate interconnect comprising a dummy gate stack comprising a dummy gate metal layer, and wherein the dummy gate stack has a height that is less than a height of the active gate stack. ### Claim 18 (depends on 17) The semiconductor device of claim 17, wherein the dummy gate stack further comprises a conductor silicide located directly on top of the dummy gate metal layer. ### Claim 19 (depends on 17) The semiconductor device of claim 17, wherein the dummy gate interconnect overlaps a shallow trench isolation (STI) region of the semiconductor device. ### Claim 20 (depends on 17) The semiconductor device of claim 17, wherein the dummy gate interconnect further comprises nitride spacers located on either side of the dummy gate stack.