# US 2014/0191287 A1 · Compressive strained iii-v complementary metal oxide semiconductor (cmos) device

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- Number: US 2014/0191287 A1
- Document ID: US20140191287A1
- Status: Published application
- Kind: A1
- Application number: 14/027,563
- Filed: 2013-09-16
- Published: 2014-07-10
- Earliest claimed: 2013-01-08
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Thomas N. Adam; Kangguo Cheng; Bruce B. Doris; Pouya Hashemi; Ali Khakifirooz; Alexander Reznicek
- Web page: https://patentgrep.com/patent/US20140191287A1

## CPC

- H10D 30/47: having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 30/4755: {having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs}
- H10D 30/751: {having composition variations in the channel regions}
- H10D 62/824: comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
- H10D 64/511: {for IGFETs}
- H10D 84/01: Manufacture or treatment
- H10D 84/0158: {the components including FinFETs}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/05: using Group III-V technology
- H10D 84/08: using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies
- H10D 86/011: {comprising FinFETs}
- H10D 86/215: {comprising FinFETs}
- H10D 62/85: being Group III-V materials, e.g. GaAs
- H10D 64/68: characterised by the insulator, e.g. by the gate insulator
- H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device including a first lattice dimension III-V semiconductor layer present on a semiconductor substrate, and a second lattice dimension III-V semiconductor layer that present on the first lattice dimension III-V semiconductor layer, wherein the second lattice dimension III-V semiconductor layer has a greater lattice dimension than the first lattice dimension III-V semiconductor layer, and the second lattice dimension III-V semiconductor layer has a compressive strain present therein. A gate structure is present on a channel portion of the second lattice dimension III-V semiconductor layer, wherein the channel portion of second lattice dimension III-V semiconductor layer has the compressive strain. A source region and a drain region are present on opposing sides of the channel portion of the second lattice dimension III-V semiconductor layer.

## Claims

### Claim 1

A semiconductor device comprising:
a first lattice dimension III-V semiconductor layer present on a semiconductor substrate, and a second lattice dimension III-V semiconductor layer that present on the first lattice dimension III-V semiconductor layer, wherein the second lattice dimension III-V semiconductor layer has a greater lattice dimension than the first lattice dimension III-V semiconductor layer, and the second lattice dimension IIII-V semiconductor layer has a compressive strain present therein;
a gate structure present on a channel portion of the second lattice dimension III-V semiconductor layer, wherein the channel portion of second lattice dimension III-V semiconductor layer has the compressive strain; and
a source region and a drain region on opposing sides of the channel portion of the second lattice dimension III-V semiconductor layer.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein a first lattice dimension for the first lattice dimension III-V semiconductor layer ranges from 5.48 Å to 6.48 Å, and a second lattice dimension for the second lattice dimension III-V semiconductor layer ranges from 5.48 Å to 6.48 Å.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the first lattice dimension III-V semiconductor layer comprises InyAl1-yAs, wherein y ranges from 0 to 1, and the second lattice dimension III-V semiconductor layer comprises InzGa1-zAs, wherein z ranges from 0 to 1.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the semiconductor device is a p-type field effect transistor.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein the gate structure includes at least one gate conductor on at least one gate dielectric, and the source region and the drain region are doped to a p-type conductivity.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the semiconductor device is a p-type fin field effect transistor (p-type finFET) and at least the second lattice dimension III-V semiconductor layer is a fin structure.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein the source region and the drain region that are present on opposing sides of the gate structure are doped to a p-type conductivity.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the semiconductor device is a p-type field effect transistor.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the gate structure includes at least one gate conductor on at least one gate dielectric, and the source region and the drain region are doped to a p-type conductivity.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, wherein the semiconductor device is a high electron mobility transistor (HEMT) comprising:
a gate stack comprised of at least one semiconductor material having a different band gap than the second lattice dimension III-V semiconductor layer on the channel portion of the second lattice dimension III-V semiconductor layer; and
a source region and a drain region on opposing sides of the channel portion of the second lattice dimension III-V semiconductor layer, wherein the source region and the drain region are doped to a p-type conductivity.

### Claim 11

A semiconductor device comprising:
a first lattice dimension III-V semiconductor layer present on a semiconductor substrate, and a second lattice dimension III-V semiconductor layer present on the first lattice dimension III-V semiconductor layer, wherein the second lattice dimension III-V semiconductor layer has a greater lattice dimension than the first lattice dimension III-V semiconductor layer, and the second lattice dimension IIII-V semiconductor layer has a compressive strain present therein;
a first gate structure for a p-type conductivity semiconductor device present on a first channel portion of the second lattice dimension III-V semiconductor layer, wherein the first channel portion of second lattice dimension III-V semiconductor layer has the compressive strain; and
a second gate structure for an n-type conductivity semiconductor device is present on a second channel portion of the second lattice dimension III-V semiconductor layer.