# US 2014/0191286 A1 · Compressive strained iii-v complementary metal oxide semiconductor (cmos) device

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- Number: US 2014/0191286 A1
- Document ID: US20140191286A1
- Status: Published application
- Kind: A1
- Application number: 13/736,183
- Filed: 2013-01-08
- Published: 2014-07-10
- Earliest claimed: 2013-01-08
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Thomas N. Adam; Kangguo Cheng; Bruce B. Doris; Pouya Hashemi; Ali Khakifirooz; Alexander Reznicek
- Web page: https://patentgrep.com/patent/US20140191286A1

## CPC

- H10D 30/47: having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 30/4755: {having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs}
- H10D 30/751: {having composition variations in the channel regions}
- H10D 62/824: comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
- H10D 64/511: {for IGFETs}
- H10D 84/01: Manufacture or treatment
- H10D 84/0158: {the components including FinFETs}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/05: using Group III-V technology
- H10D 84/08: using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies
- H10D 86/011: {comprising FinFETs}
- H10D 86/215: {comprising FinFETs}
- H10D 62/85: being Group III-V materials, e.g. GaAs
- H10D 64/68: characterised by the insulator, e.g. by the gate insulator
- H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device including a first lattice dimension III-V semiconductor layer present on a semiconductor substrate, and a second lattice dimension III-V semiconductor layer that present on the first lattice dimension III-V semiconductor layer, wherein the second lattice dimension III-V semiconductor layer has a greater lattice dimension than the first lattice dimension III-V semiconductor layer, and the second lattice dimension III-V semiconductor layer has a compressive strain present therein. A gate structure is present on a channel portion of the second lattice dimension III-V semiconductor layer, wherein the channel portion of second lattice dimension III-V semiconductor layer has the compressive strain. A source region and a drain region are present on opposing sides of the channel portion of the second lattice dimension III-V semiconductor layer.

## Claims

### Claim 1

A method of forming a semiconductor device comprising:
forming a first III-V semiconductor layer on a semiconductor substrate;
forming a second III-V semiconductor layer on the first III-V semiconductor layer, wherein the second III-V semiconductor layer has a bottommost surface that is in direct physical contact with a topmost surface of said first III-V semiconductor layer and has a greater lattice dimension than the first III-V semiconductor layer, wherein a compressive strain is formed in the second III-V semiconductor layer; and
forming a p-type semiconductor device on the second III-V semiconductor layer having the compressive strain.

### Claim 2 (depends on 1)

The method of claim 1, wherein the semiconductor substrate comprises Si, GaAs, InP or a combination thereof.

### Claim 3 (depends on 1)

The method of claim 1, wherein at least one of the first III-V semiconductor layer and the second III-V semiconductor layer are deposited using an epitaxial deposition process.

### Claim 4 (depends on 1)

The method of claim 1, wherein a first lattice dimension for the first III-V semiconductor layer ranges from 5.48 Å to 6.48 Å, and a second lattice dimension for the second III-V semiconductor layer ranges from 5.48 Å to 6.48 Å.

### Claim 5 (depends on 1)

The method of claim 1, wherein the first III-V semiconductor layer comprising InyAl1-yAs, wherein y ranges from 0 to 1, and the second III-V semiconductor layer comprises InzGa1-zAs, wherein z ranges from 0 to 1.

### Claim 6 (depends on 4)

The method of claim 4, further comprising forming a GaAs nucleation layer on the semiconductor substrate and an InxAl1-xAs buffer layer on the GaAs nucleation layer, wherein X=0-Y.

### Claim 7 (depends on 6)

The method of claim 6, wherein the GaAs nucleation layer and the InxAl1-xAs buffer layer are formed using an epitaxial deposition process.

### Claim 8 (depends on 1)

The method of claim 1, wherein the forming of the semiconductor device on the second III-V semiconductor layer comprises forming a field effect transistor (FET) comprising:
forming a gate structure on a channel portion of the second III-V semiconductor layer; and
forming a source region and a drain region on opposing sides of the channel portion of the second IIII-V semiconductor layer.

### Claim 9 (depends on 1)

The method of claim 1, wherein the forming of the semiconductor device comprises forming a high electron mobility transistor (HEMT) comprising:
forming a gate stack comprised of at least one semiconductor material having a different band gap than the second III-V semiconductor layer on the channel portion of the second III-V semiconductor layer; and
forming a source region and a drain region on opposing sides of the channel portion of the second IIII-V semiconductor layer.

### Claim 10 (depends on 1)

The method of claim 1, wherein forming the semiconductor device comprises:
etching the second III-V semiconductor layer and the first III-V semiconductor layer to form a fin structure; and
forming a gate structure on the channel portion of the fin structure; and
forming a source region and a drain region on opposing sides of the channel portion of the fin structure.

### Claim 11

A method of forming a semiconductor device comprising:
forming a first III-V semiconductor layer on a semiconductor substrate;
forming a second III-V semiconductor layer on the first III-V semiconductor layer, wherein the second III-V semiconductor layer has a bottommost surface that is in direct physical contact with a topmost surface of said first III-V semiconductor layer and has a greater lattice constant than the first III-V semiconductor layer, wherein a compressive strain is formed in the second III-V semiconductor layer;
forming a p-type semiconductor device on a first portion of the second III-V semiconductor layer having the compressive strain; and
forming an n-type semiconductor device on a second portion of the second III-V semiconductor layer.

### Claim 12 (depends on 11)

The method of claim 11, further comprising forming a GaAs nucleation layer on the semiconductor substrate and an InxAl1-xAs buffer layer on the GaAs nucleation layer, wherein X=0-Y.

### Claim 13 (depends on 11)

The method of claim 11, wherein said forming said p-type semiconductor device on said first portion of said second III-V semiconductor layer comprises:
forming a first gate structure on a first channel portion of the first portion of the second III-V semiconductor layer;
forming a p-type source region and a p-type drain region on opposing sides of the first channel portion of the first portion of the second IIII-V semiconductor layer; and wherein forming the n-type semiconductor device on a second portion of the second III-V semiconductor layer:
forming a second gate structure on a second channel portion of the second portion of the second III-V semiconductor layer; and
forming an n-type source region and an n-type drain region on opposing sides of the second channel portion of the second portion of the second III-V semiconductor layer.

### Claim 14 (depends on 11)

The method of claim 11, wherein the forming of the p-type semiconductor device on a first portion of the second III-V semiconductor layer having the compressive strain comprises forming a first high electron mobility transistor (HEMT) device comprising:
forming a first gate stack comprised of at least one first semiconductor material having a different band gap than the second III-V semiconductor layer on a first channel portion of the first portion of the second III-V semiconductor layer, and
forming a p-type source region and a p-type drain region on opposing sides of the first channel portion of the first portion of the second IIII-V semiconductor layer; and
the forming of the n-type semiconductor device on a second portion of the second III-V semiconductor layer comprises forming a second first high electron mobility transistor (HEMT) device comprising:
forming a second gate stack comprised of at least one second semiconductor material having a different band gap than the second III-V semiconductor layer on a second channel portion of the second portion of the second III-V semiconductor layer, and
forming an n-type source region and an n-type drain region on opposing sides of the first channel portion of the second portion of the second IIII-V semiconductor layer.

### Claim 15 (depends on 11)

The method of claim 11, further comprising etching at least the second III-V semiconductor layer to form a first fin structure and a second fin structure, wherein the forming of the p-type semiconductor device on a first portion of the second III-V semiconductor layer comprises forming a first gate structure on a first channel portion of the first fin structure, and forming a p-type source region and a p-type drain region on opposing sides of the first channel portion of the first fin structure, wherein the forming of the n-type semiconductor device on the second portion of the second III-V semiconductor layer comprises forming a second gate structure on a second channel portion of the second fin structure, and forming an n-type source region and an n-type drain region on opposing sides of the second channel portion of the second fin structure.

### Claim at position 16

-23. (canceled)

### Claim 25

(canceled)

### Claim 26 (depends on 1)

The method of claim 1, wherein an entirety of a bottommost surface of a gate dielectric material of said p-type semiconductor device directly contacts a topmost surface of said second III-V semiconductor layer

### Claim 27 (depends on 11)

The method of claim 11, wherein an entirety of a bottommost surface of a gate dielectric material of said p-type semiconductor device directly contacts a topmost surface of said second III-V semiconductor layer

### Claim 28

A method of forming a semiconductor device comprising:
providing a semiconductor substrate;
forming a GaAs nucleation layer on the semiconductor substrate and an InxAl1-xAs buffer layer on the GaAs nucleation layer, wherein X=0-Y.
forming a first III-V semiconductor layer on the buffer layer;
forming a second III-V semiconductor layer on the first III-V semiconductor layer, wherein the second III-V semiconductor layer has a greater lattice dimension than the first III-V semiconductor layer, wherein a compressive strain is formed in the second III-V semiconductor layer; and
forming a p-type semiconductor device on the second III-V semiconductor layer having the compressive strain.

### Claim 29

A method of forming a semiconductor device comprising:
providing a semiconductor substrate;
forming a GaAs nucleation layer on the semiconductor substrate and an InxAl1-xAs buffer layer on the GaAs nucleation layer, wherein X=0-Y;
forming a first III-V semiconductor layer on the buffer layer;
forming a second III-V semiconductor layer on the first III-V semiconductor layer, wherein the second III-V semiconductor layer has a greater lattice constant than the first III-V semiconductor layer, wherein a compressive strain is formed in the second III-V semiconductor layer;
forming a p-type semiconductor device on a first portion of the second III-V semiconductor layer having the compressive strain; and
forming an n-type semiconductor device on a second portion of the second semiconductor layer.