# US 2014/0191256 A1 · Thin film trannsistor array panel and manufacturing method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0191256 A1 - Document ID: US20140191256A1 - Status: Published application - Kind: A1 - Application number: 14/090,487 - Filed: 2013-11-26 - Published: 2014-07-10 - Earliest claimed: 2013-01-10 - Assignees: Samsung Display Co., Ltd. - Applicants: Samsung Display Co., Ltd. - Inventors: Jeong Min PARK; Ji-Hyun KIM; Jung-Soo LEE; Sung Kyun PARK - Web page: https://patentgrep.com/patent/US20140191256A1 ## CPC - H10D 86/60: wherein the TFTs are in active matrices - G02F 1/13458: {Terminal pads} - G02F 1/136227: {Through-hole connection of the pixel electrode to the active element through an insulation layer} - G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} - H10D 30/6732: {Bottom-gate only TFTs} - H10D 30/6745: {Polycrystalline or microcrystalline silicon} - H10D 30/6746: {Amorphous silicon} - H10D 86/441: {Interconnections, e.g. scanning lines} - H10D 86/451: {characterised by the compositions or shapes of the interlayer dielectrics} - H10H 20/855: Optical field-shaping means, e.g. lenses - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS - H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS ## Abstract Instead of forming contact holes the same way in both the non-image forming peripheral area (PA) and the image forming display area of a thin film transistor array panel, contact holes in the DA are formed to be substantially smaller than those in the PA for thereby improving an aperture ratio of the corresponding display device. In an exemplary embodiment, an inorganic gate insulating layer is not etched in the DA and only an inorganic first passivation layer among inorganic insulating layers positioned in the DA is etched to allow communication between the drain electrode and the corresponding field generating electrode. On the other hand, in the peripheral area, plural inorganic insulating layers such as the gate insulating laver, the first passivation laver, and the second passivation layer positioned on the gate wire and the data wire are simultaneously etched to form second contact holes and third contact holes exposing respective gate pads and data pads. ## Claims ### Claim 1 A thin film transistor array panel for use in a display device and comprising: a substrate having a display area through which image forming light rays of the display device will pass and a peripheral area disposed near the display area and through which image forming light rays of the display device will not pass; a gate line positioned in the display area of the substrate; a gate pads connected to the gate line and positioned in the peripheral area of the substrate; a gate insulating layer positioned on the gate line and the gate pad; a data line and a drain electrode positioned in the display area of the substrate; a data pad connected to the data line and positioned in the peripheral area of the substrate and on the gate insulating layer; a first passivation layer having a first contact hole defined therethrough for exposing a portion of the drain electrode; a first field generating electrode connected to the drain electrode through the first contact hole of the first passivation layer; a second passivation layer positioned on the first field generating electrode; and a second field generating electrode positioned on the second passivation layer, wherein the first field generating electrode include a portion positioned in the first contact hole covered by the second passivation layer, wherein the gate insulating layer, the first passivation layer, and the second passivation layer have second contact hole extending therethrough and positioned in the peripheral area for exposing the gate pad, and wherein the first passivation layer and the second passivation layer have a third contact hole extending therethrough and positioned in the peripheral area for exposing the data pad. ### Claim 2 (depends on 1) The thin film transistor array panel of claim 1, further comprising an organic layer positioned between the first passivation layer and the second passivation layer. ### Claim 3 (depends on 2) The thin film transistor array panel of claim 2, wherein the organic layer includes one or more color filters. ### Claim 4 (depends on 2) The thin film transistor array panel of claim 2, wherein the organic layer is positioned in the display area and is not positioned in the peripheral area. ### Claim 5 (depends on 2) The thin film transistor array panel of claim 2, wherein the organic layer is positioned in the display area and the peripheral area, and a thickness of the portion of the organic layer positioned in the peripheral area is thinner than the thickness of the portion of the organic layer positioned in the display area. ### Claim 6 (depends on 2) The thin film transistor array panel of claim 2, wherein at least one of the first field generating electrode and the second field generating electrode is subdivided to have a plurality of spaced apart branch electrodes. ### Claim 7 (depends on 2) The thin film transistor array panel of claim 2, wherein the first contact hole overlaps a portion of the gate line that does not overlap the drain electrode, and a portion of the gate line overlapped by the first contact hole is covered by the gate insulating layer. ### Claim 8 (depends on 1) The thin film transistor array panel of claim 1, wherein one of the first field generating electrode and the second field generating electrode has a plurality of branch electrodes. ### Claim 9 (depends on 1) The thin film transistor array panel of claim 1, wherein the first contact hole overlap a portion of the gate line that does not overlap the drain electrode, and the portion of the gate line overlapped by the first contact hole are covered by the gate insulating layer. ### Claim 10 A method of manufacturing a thin film transistor array panel for use in a display device, the method comprising: providing a substrate having a peripheral area and a display area, where the display area is one through which image forming light rays of the display device will pass and the peripheral area is one through which image forming light rays of the display device will not pass; forming a gate line in the display area of the substrate and a gate pad in the peripheral area of the substrate; forming a gate insulating layer on the gate line and the gate pad; forming a data line and a drain electrode in the display area of the substrate and a data pad in the peripheral area of the substrate; depositing a first passivation layer in the peripheral area and in the display area of the substrate; etching the first passivation layer to form a first contact hole exposing a portion of the drain electrode; forming a first field generating electrode connected to the drain electrode through the first contact hole; depositing a second passivation layer on the first field generating electrode; etching the gate insulating layer, the first passivation layer, and the second passivation layer positioned in the peripheral area to form a second contact hole exposing the gate pad, and etching the first passivation layer and the second passivation layer to form a third contact hole exposing the data pad; and forming a second field generating electrode on the second passivation layer; wherein the first contact hole is narrower than either of the second and third contact holes. ### Claim 11 (depends on 10) The method of claim 10, wherein the formation of the first contact hole exposing the drain electrode in the first passivation layer includes: forming an organic layer having an opening on the first passivation layer; and etching the first passivation layer by using the organic layer as an etching mask. ### Claim 12 (depends on 11) The method of claim 11, wherein the formation of the first contact hole exposing the drain electrode in the first passivation layer includes polishing the organic layer after etching the first passivation layer. ### Claim 13 (depends on 11) The method of claim 11, wherein the formation of the organic layer includes forming a color filter on the first passivation layer. ### Claim 14 (depends on 11) The method of claim 11, wherein the organic layer is only formed in the display area and is not formed in the peripheral area. ### Claim 15 (depends on 11) The method of claim 11, wherein a thickness of a portion of the organic layer positioned in the peripheral area is thinner than the thickness of a portion of the organic layer positioned in the display area. ### Claim 16 (depends on 10) The method of claim 10, wherein the formation of the first contact hole exposing the drain electrode in the first passivation layer includes: forming the organic layer on the first passivation layer; forming a photosensitive film pattern on the organic layer; and etching the first passivation layer by using the photosensitive film pattern as an etching mask. ### Claim 17 (depends on 16) The method of claim 16, wherein the formation of the first contact hole exposing the drain electrode in the first passivation layer includes removing the photosensitive film pattern after etching the first passivation layer. ### Claim 18 (depends on 16) The method of claim 16, wherein the formation of the organic layer includes forming a color filter on the first passivation layer. ### Claim 19 (depends on 16) The method of claim 16, wherein the organic layer is formed in the display area and is not formed in the peripheral area. ### Claim 20 (depends on 16) The method of claim 16, wherein a thickness of a portion of the organic layer positioned in the peripheral area is thinner than the thickness of a portion of the organic layer positioned in the display area.