# US 2014/0191252 A1 · Complementary metal oxide semiconductor device, optical apparatus including the same, and method of manufacturing the same

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- Number: US 2014/0191252 A1
- Document ID: US20140191252A1
- Status: Published application
- Kind: A1
- Application number: 13/974,233
- Filed: 2013-08-23
- Published: 2014-07-10
- Earliest claimed: 2013-01-07
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Sang-moon LEE; Young-jin CHO
- Web page: https://patentgrep.com/patent/US20140191252A1

## CPC

- H10D 84/08: using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies
- H10D 62/82: Heterojunctions
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 62/85: being Group III-V materials, e.g. GaAs
- H10D 84/01: Manufacture or treatment
- H10D 84/0165: {the components including complementary IGFETs, e.g. CMOS devices}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS}
- H10H 29/10: Integrated devices comprising at least one light-emitting semiconductor component covered by group H10H20/00 (active-matrix LED displays H10H29/30)
- H10P 14/2905: {Silicon, silicon germanium or germanium}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3414: {being group IIIA-VIA materials}
- H10P 52/402: {of semiconductor materials}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A complementary metal oxide semiconductor (CMOS) device includes an n-type first transistor on a silicon substrate, the n-type first transistor including a Group III-V compound semiconductor substrate, and a p-type second transistor on the silicon substrate, the p-type second transistor including a germanium based substrate.

## Claims

### Claim 1

A complementary metal oxide semiconductor (CMOS) device comprising:
a n-type first transistor on a silicon substrate, the n-type first transistor including a first substrate, the first substrate including a Group III-V compound semiconductor; and
a p-type second transistor on the silicon substrate, the p-type second transistor including a second substrate, the second substrate including germanium.

### Claim 2 (depends on 1)

The CMOS device of claim 1, wherein the n-type first transistor comprises:
a channel layer on the first substrate;
a source electrode on the channel layer;
a drain electrode on the channel layer and spaced apart from the source electrode; and
a gate stacked structure on the channel layer between the source electrode and the drain electrode.

### Claim 3 (depends on 1)

The CMOS device of claim 1, wherein the p-type second transistor comprises:
a first impurity area in the second substrate;
a second impurity area in the second substrate and spaced apart from the first impurity area; and
a gate stacked structure on the second substrate between the first impurity area and the second impurity area.

### Claim 4 (depends on 1)

The CMOS device of claim 1, wherein the first substrate is one of a binary compound semiconductor substrate and a multicomponent compound semiconductor substrate including at least one of arsenic (As), phosphorus (P), and antimony (Sb).

### Claim 5 (depends on 1)

The CMOS device of claim 1, wherein the second substrate is one of a germanium (Ge) substrate and a silicon-germanium (SiGe) substrate.

### Claim 6 (depends on 1)

The CMOS device of claim 1, wherein one of the first and second substrates is surrounded by the other one of the first and second substrates.

### Claim 7

An optical apparatus comprising:
a CMOS device on a silicon substrate, the CMOS device including,
a n-type first transistor including a first substrate, the first substrate including a Group III-V compound semiconductor, and
a p-type second transistor including a second substrate, the second substrate including germanium; and
an optical device on the silicon substrate separate from the CMOS device.

### Claim 8 (depends on 7)

The optical apparatus of claim 7, wherein the optical device is one of a light emitting diode (LED) and a laser diode (LD), and includes a Group III-V compound semiconductor.

### Claim 9 (depends on 7)

The optical apparatus of claim 7, wherein the optical device is a light receiving device, and includes a germanium (Ge) based semiconductor layer.

### Claim 10 (depends on 7)

The optical apparatus of claim 7, wherein one of the first and second substrates is surrounded by the other one of the first and second substrates.

### Claim 11

A method of manufacturing a CMOS device, the method comprising:
forming a first substrate on a silicon substrate;
exposing a portion of the silicon substrate by removing a portion of the first substrate;
forming a second substrate on the exposed portion of the silicon substrate, the second substrate insulated from the first substrate;
forming a first transistor on one of the first and second substrates; and
forming a second transistor on the other one of the first and second substrates,
wherein one of the first and second substrates is a Group III-V compound semiconductor substrate, and the other one of the first and second substrates is a germanium based substrate.

### Claim 12 (depends on 11)

The method of claim 11, wherein the forming a second substrate comprises:
forming an insulating layer to cover a surface of the first substrate and the exposed portion of the silicon substrate;
removing the insulating layer from the exposed portion of the silicon substrate; and
forming the second substrate on the exposed portion of the silicon substrate after the removing the insulating layer.

### Claim 13 (depends on 11)

The method of claim 11, wherein the forming a first transistor comprises:
forming a channel layer on one of the first and second substrates;
forming a source electrode and a drain electrode on the channel layer, the source electrode and the drain electrode spaced apart from each other; and
forming a gate stacked structure on the channel layer between the source electrode and the drain electrode.

### Claim 14 (depends on 11)

The method of claim 11, wherein the forming a second transistor comprises:
forming a gate stacked structure on one of the first and second substrates; and
forming an impurity area in the one of the first and second substrates on both sides of the gate stacked structure.

### Claim 15 (depends on 11)

The method of claim 11, wherein the forming a second substrate comprises:
forming the second substrate on the first substrate; and
planarizing the second substrate to have a same height as the first substrate.

### Claim 16 (depends on 11)

The method of claim 11, wherein the forming a first substrate forms one of a binary compound semiconductor substrate and a multicomponent compound semiconductor substrate including at least one of As, P, and Sb.

### Claim 17 (depends on 11)

The method of claim 11, wherein the forming a second substrate forms one of a germanium (Ge) substrate and a silicon-germanium (SiGe) substrate.

### Claim 18 (depends on 11)

The method of claim 11, wherein the forming a second substrate forms a base of the second substrate to be lower or higher than a base of the first substrate.

### Claim 19 (depends on 18)

The method of claim 18, wherein the forming a base of the second substrate forms the second substrate to be lower than the base of the first substrate by removing a portion of the silicon substrate from the exposed portion of the silicon substrate.

### Claim 20 (depends on 18)

The method of claim 18, wherein the forming a base of the second substrate forms the second substrate to be higher than the base of the first substrate by increasing a thickness of the silicon substrate in the exposed portion of the silicon substrate.