# US 2014/0191247 A1 · Semiconductor device

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- Number: US 2014/0191247 A1
- Document ID: US20140191247A1
- Status: Published application
- Kind: A1
- Application number: 14/143,332
- Filed: 2013-12-30
- Published: 2014-07-10
- Earliest claimed: 2013-01-09
- Assignees: Kabushiki Kaisha Toshiba
- Applicants: Kabushiki Kaisha Toshiba
- Inventors: Ryosuke IIJIMA; Tatsuo Shimizu; Johji Nishio
- Web page: https://patentgrep.com/patent/US20140191247A1

## CPC

- H10D 62/8325: {Silicon carbide}
- H10D 12/031: {of IGBTs}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/66: Vertical DMOS [VDMOS] FETs
- H10D 30/794: {comprising conductive materials, e.g. silicided source, drain or gate electrodes}
- H10D 62/117: {Shapes of semiconductor bodies}
- H10D 62/40: Crystalline structures
- H10D 64/252: {for vertical or pseudo-vertical devices}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 62/405: {Orientations of crystalline planes}
- H10D 64/0115: {to silicon carbide}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

According to one embodiment, a semiconductor device includes a gate electrode, a first semiconductor region, a second semiconductor region of a first conductivity type, a third semiconductor region of a second conductivity type and a fourth semiconductor region of the first conductivity type. The first semiconductor region includes a silicon carbide crystal of 4H—SiC. The second semiconductor region includes a first portion opposing the gate electrode and is provided between the gate electrode and the first semiconductor region. The third semiconductor region has a lattice spacing different from a lattice spacing of the silicon carbide crystal of 4H—SiC and is provided between the gate electrode and the second semiconductor region. The fourth semiconductor region is selectively provided on the third semiconductor region.

## Claims

### Claim 1

A semiconductor device comprising:
a gate electrode;
a first semiconductor region including a silicon carbide crystal of 4H—SiC;
a second semiconductor region of a first conductivity type including a first portion opposing the gate electrode, and the second semiconductor region being provided between the gate electrode and the first semiconductor region;
a third semiconductor region of a second conductivity type having a lattice spacing different from a lattice spacing of the silicon carbide crystal of 4H—SiC, and the third semiconductor region being provided between the gate electrode and the second semiconductor region; and
a fourth semiconductor region of the first conductivity type selectively provided on the third semiconductor region.

### Claim 2 (depends on 1)

The device according to claim 1, further comprising:
a gate insulating film provided on a surface of the third semiconductor region, on a portion of a surface of the second semiconductor region being in contact with the third semiconductor region, and on at least a portion of a surface of the fourth semiconductor region being in contact with the third semiconductor region,
the gate insulating film being in contact with a semiconductor layer,
the semiconductor layer including the second semiconductor region, the third semiconductor region and the fourth semiconductor region,
a surface of the semiconductor layer being a (0001) crystal plane, and
the lattice spacing in a <11-20> direction of the silicon carbide crystal in the third semiconductor region being in contact with the gate insulating film being longer than the lattice spacing in a <11-20> direction of the silicon carbide crystal in the first semiconductor region.

### Claim 3 (depends on 1)

The device according to claim 1, further comprising:
a gate insulating film provided on a surface of the third semiconductor region, on a portion of a surface of the second semiconductor region being in contact with the third semiconductor region, and on at least a portion of a surface of the fourth semiconductor region being in contact with the third semiconductor region,
the gate insulating film being in contact with a semiconductor layer,
the semiconductor layer including the second semiconductor region, the third semiconductor region and the fourth semiconductor region,
a surface of the semiconductor layer being a (000-1) crystal plane, and
the lattice spacing in a <11-20> direction of the silicon carbide crystal in the third semiconductor region being in contact with the gate insulating film being longer than the lattice spacing in a <11-20> direction of the silicon carbide crystal in the first semiconductor region.

### Claim 4 (depends on 1)

The device according to claim 1, further comprising:
a gate insulating film provided on a surface of the third semiconductor region, on a portion of a surface of the second semiconductor region being in contact with the third semiconductor region, and on at least a portion of a surface of the fourth semiconductor region being in contact with the third semiconductor region,
the gate insulating film being in contact with a semiconductor layer,
the semiconductor layer including the second semiconductor region, the third semiconductor region and the fourth semiconductor region,
a surface of the semiconductor layer being a (0001) crystal plane, and
the lattice spacing in a <1-100> direction of the silicon carbide crystal in the third semiconductor region being in contact with the gate insulating film being shorter than the lattice spacing in a <1-100> direction of the silicon carbide crystal in the first semiconductor region.

### Claim 5 (depends on 1)

The device according to claim 1, further comprising:
a gate insulating film provided on a surface of the third semiconductor region, on a portion of a surface of the second semiconductor region being in contact with the third semiconductor region, and on at least a portion of a surface of the fourth semiconductor region being in contact with the third semiconductor region,
the gate insulating film being in contact with a semiconductor layer,
the semiconductor layer including the second semiconductor region, the third semiconductor region and the fourth semiconductor region,
a surface of the semiconductor layer being a (000-1) crystal plane, and
the lattice spacing in a <1-100> direction of the silicon carbide crystal in the third semiconductor region being in contact with the gate insulating film being shorter than the lattice spacing in a <1-100> direction of the silicon carbide crystal in the first semiconductor region.

### Claim 6 (depends on 1)

The device according to claim 1, further comprising:
a gate insulating film provided on a surface of the third semiconductor region, on a portion of a surface of the second semiconductor region being in contact with the third semiconductor region, and on at least a portion of a surface of the fourth semiconductor region being in contact with the third semiconductor region,
a portion of the third semiconductor region being in contact with the gate insulating film is the third semiconductor region within at least 3 nm from a boundary between the third semiconductor region and the gate insulating film toward a side of the first semiconductor region.

### Claim 7 (depends on 1)

The device according to claim 1, further comprising:
a silicon containing layer connected to the first semiconductor region.

### Claim 8 (depends on 7)

The device according to claim 7, wherein
the silicon containing layer includes nickel silicon.

### Claim 9 (depends on 2)

The device according to claim 2, wherein
on a surface of the semiconductor layer being in contact with the gate insulating film, a boundary between the fourth semiconductor region and the third semiconductor region is orthogonal to the <11-20> direction.

### Claim 10 (depends on 2)

The device according to claim 2, wherein
on a surface of the semiconductor layer being in contact with the gate insulating film, a boundary between the third semiconductor region and the second semiconductor region is orthogonal to the <11-20> direction.

### Claim 11 (depends on 2)

The device according to claim 2, wherein
on a surface of the semiconductor layer being in contact with the gate insulating film, a direction from the fourth semiconductor region toward the second semiconductor region is parallel to the <11-20> direction.

### Claim 12 (depends on 3)

The device according to claim 3, wherein
on a surface of the semiconductor layer being in contact with the gate insulating film, a boundary between the fourth semiconductor region and the third semiconductor region is orthogonal to the <11-20> direction.

### Claim 13 (depends on 3)

The device according to claim 3, wherein
on a surface of the semiconductor layer being in contact with the gate insulating film, a boundary between the third semiconductor region and the second semiconductor region is orthogonal to the <11-20> direction.

### Claim 14 (depends on 3)

The device according to claim 3, wherein
on a surface of the semiconductor layer being in contact with the gate insulating film, a direction from the fourth semiconductor region toward the second semiconductor region is parallel to the <11-20> direction.

### Claim 15 (depends on 4)

The device according to claim 4, wherein
on a surface of the semiconductor layer being in contact with the gate insulating film, a boundary between the fourth semiconductor region and the third semiconductor region is orthogonal to the <11-20> direction.

### Claim 16 (depends on 4)

The device according to claim 4, wherein
on a surface of the semiconductor layer being in contact with the gate insulating film, a boundary between the third semiconductor region and the second semiconductor region is orthogonal to the <11-20> direction.

### Claim 17 (depends on 4)

The device according to claim 4, wherein
on a surface of the semiconductor layer being in contact with the gate insulating film, a direction from the fourth semiconductor region toward the second semiconductor region is parallel to the <11-20> direction.

### Claim 18 (depends on 5)

The device according to claim 5, wherein
on a surface of the semiconductor layer being in contact with the gate insulating film, a boundary between the fourth semiconductor region and the third semiconductor region is orthogonal to the <11-20> direction.

### Claim 19 (depends on 5)

The device according to claim 5, wherein
on a surface of the semiconductor layer being in contact with the gate insulating film, a boundary between the third semiconductor region and the second semiconductor region is orthogonal to the <11-20> direction.

### Claim 20 (depends on 5)

The device according to claim 5, wherein
on a surface of the semiconductor layer being in contact with the gate insulating film, a direction from the fourth semiconductor region toward the second semiconductor region is parallel to the <11-20> direction.