# US 2014/0191246 A1 · Bonding transistor wafer to led wafer to form active led modules

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- Number: US 2014/0191246 A1
- Document ID: US20140191246A1
- Status: Published application
- Kind: A1
- Application number: 14/207,047
- Filed: 2014-03-12
- Published: 2014-07-10
- Earliest claimed: 2013-01-09
- Assignees: Nthdegree Technologies Worldwide Inc.
- Applicants: Nthdegree Technologies Worldwide Inc.
- Inventors: Bradley S. Oraw
- Web page: https://patentgrep.com/patent/US20140191246A1

## CPC

- H10W 90/00: Package configurations
- H10H 20/018: {Bonding of wafers}
- H10H 20/019: {Removal of at least a part of a substrate on which semiconductor layers have been formed}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS

## Abstract

LED modules are disclosed having a control MOSFET, or other transistor, in series with an LED. In one embodiment, a MOSFET wafer, containing an array of vertical MOSFETS, is aligned and bonded to an LED wafer, containing a corresponding array of vertical LEDs, and singulated to form thousands of active 3-terminal LED modules with the same footprint as a single LED. Despite the different forward voltages of red, green, and blue LEDs, RGB modules may be connected in parallel and their control voltages staggered at 60 Hz or greater to generate a single perceived color, such as white. The RGB modules may be connected in a panel for general illumination or for a color display.

## Claims

### Claim 1

An integrated driver and light emitting diode (LED module comprising:
a vertical light emitting diode (LED) having a top LED conducting surface and a bottom LED conducting surface; and
a vertical transistor in series with the LED,
the transistor having a first terminal, a second terminal, and a third terminal, the first terminal being a bottom conducting surface of the transistor, the bottom conducting surface of the transistor being electrically and mechanically bonded to the top LED conducting surface by a conductive bonding layer,
the LED and transistor being substantially the same size,
the LED being configured to emit light when a first voltage is applied to the bottom LED conducting surface, a second voltage is applied to the second terminal, and a first control voltage is applied to the third terminal.

### Claim 2 (depends on 1)

The module of claim 1 wherein the transistor has a top surface, wherein the second terminal and third terminal are formed on the top surface.

### Claim 3 (depends on 1)

The module of claim 1 wherein the transistor is a FET.

### Claim 4 (depends on 3)

The module of claim 3 wherein the first terminal is a drain terminal, the second terminal is a gate terminal, and the third terminal is a source terminal.

### Claim 5 (depends on 3)

The module of claim 3 wherein the first terminal is a drain terminal, the second terminal is a source terminal, and the third terminal is a gate terminal.

### Claim 6 (depends on 1)

The module of claim 1 wherein the transistor is a bipolar transistor.

### Claim 7 (depends on 1)

The module of claim 1 wherein the top LED conducting surface is an anode and the bottom LED conducting surface is a cathode.

### Claim 8 (depends on 1)

The module of claim 1 wherein the top LED conducting surface is a cathode and the bottom LED conducting surface is an anode.

### Claim 9 (depends on 1)

The module of claim 1 wherein the LED is GaN-based and the transistor is silicon-based.

### Claim 10

A method of forming a lighting device comprising:
forming a first array of vertical light emitting diodes (LEDs) in an LED wafer, each of the LEDs having a top LED conducting surface and a bottom LED conducting surface; and
forming a second array of vertical transistors in a transistor wafer, each of the transistors having a first terminal, a second terminal, and a third terminal, the first terminal being a bottom conducting surface of the transistors;
aligning the LED wafer with the transistor wafer such that each transistor area in the transistor wafer is aligned with each LED area in the LED wafer;
forming bonded wafers by bonding the top LED conducting surface of the LED wafer to the bottom conducting surface of the transistor wafer to electrically and mechanically bond the top LED conducting surface to the bottom conducting surface by a bonding layer; and
singulating the bonded wafers to create individual modules, each module containing at least a driver transistor and an LED.

### Claim 11 (depends on 10)

The method of claim 10 wherein forming the first array of vertical LEDs comprises epitaxially growing LED layers over an LED growth substrate, the method further comprising removing the growth substrate after bonding the top LED conducting surface of the LED wafer to the bottom conducting surface of the transistor wafer.

### Claim 12 (depends on 10)

The method of claim 10 wherein forming the second array of vertical transistors comprises forming transistor regions over a substrate, the method further comprising removing the substrate prior to bonding the top LED conducting surface of the LED wafer to the bottom conducing surface of the transistor wafer.

### Claim 13 (depends on 12)

The method of claim 12 further comprising affixing a first carrier wafer to a top surface of the transistor wafer prior to removing the substrate.

### Claim 14 (depends on 13)

The method of claim 13 further comprising affixing a second carrier wafer to the bottom LED conducting surface, and then removing the first carrier wafer to process a top surface of the transistor wafer.

### Claim 15 (depends on 14)

The method of claim 14 further comprising etching trenches in the LED wafer and transistor wafer down to the second carrier wafer to define the individual modules, then removing the individual modules from the second carrier wafer.

### Claim 16 (depends on 14)

The method of claim 14 further comprising packaging the individual modules to form an array of modules for generating light.

### Claim 17 (depends on 16)

The method of claim 16 wherein the array of modules is part of an addressable color display.

### Claim 18 (depends on 16)

The method of claim 16 wherein the array of modules is part of a light source generating white light.