# US 2014/0191242 A1 · Method and system for a gallium nitride vertical transistor

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- Number: US 2014/0191242 A1
- Document ID: US20140191242A1
- Status: Published application
- Kind: A1
- Application number: 13/735,912
- Filed: 2013-01-07
- Published: 2014-07-10
- Earliest claimed: 2013-01-07
- Assignees: Avogy, Inc.
- Applicants: Avogy, Inc.
- Inventors: Hui Nie; Andrew P. Edwards; Isik Kizilyalli; David P. Bour; Thomas R. Prunty; Quentin Diduck
- Web page: https://patentgrep.com/patent/US20140191242A1

## CPC

- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 30/051: {of FETs having PN junction gates (H10D30/015 takes precedence)}
- H10D 30/0515: {of vertical FETs having PN homojunction gates}
- H10D 30/831: {Vertical FETs having PN junction gate electrodes (Vertical SIT H10D30/202)}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 62/824: comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 62/852: being Group III-V materials comprising three or more elements, e.g. AlGaN or InAsSbP
- H10P 14/2908: {Nitrides}
- H10P 14/3416: {Nitrides}
- H10D 62/405: {Orientations of crystalline planes}
- H10D 62/812: {Single quantum well structures}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A vertical JFET includes a GaN substrate comprising a drain of the JFET and a plurality of patterned epitaxial layers coupled to the GaN substrate. A distal epitaxial layer comprises a first part of a source channel and adjacent patterned epitaxial layers are separated by a gap having a predetermined distance. The vertical JFET also includes a plurality of regrown epitaxial layers coupled to the distal epitaxial layer and disposed in at least a portion of the gap. A proximal regrown epitaxial layer comprises a second part of the source channel. The vertical JFET further includes a source contact passing through portions of a distal regrown epitaxial layer and in electrical contact with the source channel, a gate contact in electrical contact with a distal regrown epitaxial layer, and a drain contact in electrical contact with the GaN substrate.

## Claims

### Claim 1

A method of fabricating a vertical JFET, the method comprising:
providing a III-nitride epitaxial structure including:
a III-nitride substrate; and
a plurality of epitaxial layers coupled to the III-nitride substrate;
removing a portion of the plurality of epitaxial layers to form a set of recesses extending a predetermined distance into the plurality of epitaxial layers, wherein the set of recesses are disposed between remaining portions of the plurality of epitaxial layers;
regrowing a plurality of regrown epitaxial layers coupled to at least a portion of one of the plurality of epitaxial layers and the remaining portions of the plurality of epitaxial layers, wherein one of the plurality of regrown epitaxial layers is electrically coupled to one of the plurality of epitaxial layers;
removing a portion of the plurality of regrown epitaxial layers to expose a portion of the one of the plurality of epitaxial layers;
forming a source contact electrically coupled to the one of the plurality of epitaxial layers;
forming a gate contact electrically coupled to another of the plurality of epitaxial layers; and
forming a drain contact electrically coupled to the III-nitride substrate.

### Claim 2 (depends on 1)

The method of claim 1 wherein regrowing the plurality of regrown epitaxial layers comprises:
regrowing a first epitaxial layer of a first conductivity type; and
regrowing a second epitaxial layer of a second conductivity type different from the first conductivity type.

### Claim 3 (depends on 1)

The method of claim 1 wherein at least one of the plurality of regrown epitaxial layers is a conformal layer.

### Claim 4 (depends on 1)

The method of claim 1 wherein the one of the plurality of epitaxial layers comprises a first part of the source channel and one of the regrown epitaxial layers comprises a second part of the source channel.

### Claim 5 (depends on 4)

The method of claim 4 wherein and the another of the plurality of epitaxial layers comprises a gate region of the vertical JFET.

### Claim 6 (depends on 5)

The method of claim 5 wherein the first part of the source channel is electrically shorted to the second part of the second channel and the source channel is characterized by a doping opposite to the gate region.

### Claim 7 (depends on 1)

The method of claim 1 wherein the plurality of regrown epitaxial layers are characterized by a thickness equal to the predetermined distance.

### Claim 8 (depends on 1)

The method of claim 1 wherein one of the plurality of epitaxial layers comprises at least one of n-type doped GaN or an AlGaN/GaN material forming a two dimensional electric gas (2DEG).

### Claim 9 (depends on 8)

The method of claim 8 wherein the one of the plurality of epitaxial layers comprises a first part of a source channel.

### Claim 10

A vertical JFET comprising:
a GaN substrate comprising a drain of the JFET;
a plurality of patterned epitaxial layers coupled to the GaN substrate, wherein a distal epitaxial layer with respect to the GaN substrate comprises a first part of a source channel and adjacent patterned epitaxial layers are separated by a gap having a predetermined distance;
a plurality of regrown epitaxial layers coupled to the distal epitaxial layer and disposed in at least a portion of the gap, wherein a proximal regrown epitaxial layer with respect to the GaN substrate comprises a second part of the source channel;
a source contact passing through portions of a distal regrown epitaxial layer with respect to the GaN substrate and in electrical contact with the source channel;
a gate contact in electrical contact with a distal regrown epitaxial layer with respect to the GaN substrate; and
a drain contact in electrical contact with the GaN substrate.

### Claim 11 (depends on 10)

The vertical JFET of claim 10 further comprising a second gate contact in electrical contact with a proximal epitaxial layer with respect to the GaN substrate.

### Claim 12 (depends on 10)

The vertical JFET of claim 10 wherein the plurality of patterned epitaxial layers are arrayed hexagonally.

### Claim 13 (depends on 12)

The vertical JFET of claim 12 wherein each of the plurality of patterned epitaxial layers include sidewalls substantially aligned with respect to crystal planes of the GaN substrate.

### Claim 14 (depends on 13)

The vertical JFET of claim 13 wherein the crystal planes are m-planes of the GaN substrate.

### Claim 15 (depends on 13)

The vertical JFET of claim 13 wherein the proximal regrown epitaxial layer is regrown on the sidewalls.

### Claim 16 (depends on 10)

The vertical JFET of claim 10 wherein the first part of the source channel is adjacent the source contact and the second part of the source channel is adjacent the proximal epitaxial layer.