# US 2014/0191241 A1 · Gallium nitride vertical jfet with hexagonal cell structure

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- Number: US 2014/0191241 A1
- Document ID: US20140191241A1
- Status: Published application
- Kind: A1
- Application number: 13/735,897
- Filed: 2013-01-07
- Published: 2014-07-10
- Earliest claimed: 2013-01-07
- Assignees: Avogy, Inc.
- Applicants: Avogy, Inc.
- Inventors: Andrew P. Edwards; Hui Nie; Donald R. Disney; Isik Kizilyalli
- Web page: https://patentgrep.com/patent/US20140191241A1

## CPC

- H10D 84/87: of PN-junction gate FETs
- H10D 30/0515: {of vertical FETs having PN homojunction gates}
- H10D 30/831: {Vertical FETs having PN junction gate electrodes (Vertical SIT H10D30/202)}
- H10D 62/126: {Top-view geometrical layouts of the regions or the junctions}
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 64/311: {Gate electrodes for field-effect devices}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An array of GaN-based vertical JFETs includes a GaN substrate comprising a drain of one or more of the JFETs and one or more epitaxial layers coupled to the GaN substrate. The array also includes a plurality of hexagonal cells coupled to the one or more epitaxial layers and extending in a direction normal to the GaN substrate. Sidewalls of the plurality of hexagonal cells are substantially aligned with respect to crystal planes of the GaN substrate. The array further includes a plurality of channel regions, each having a portion adjacent a sidewall of the plurality of hexagonal cells, a plurality of gate regions of one or more of the JFETs, each electrically coupled to one or more of the plurality of channel regions, and a plurality of source regions of one or more of the JFETs electrically coupled to one or more of the plurality of channel regions.

## Claims

### Claim 1

An array of GaN-based vertical JFETs comprising:
a GaN substrate comprising a drain of one or more of the JFETs;
one or more GaN epitaxial layers coupled to the GaN substrate;
a plurality of hexagonal cells coupled to the one or more GaN epitaxial layers and extending in a direction normal to the GaN substrate, wherein sidewalls of the plurality of hexagonal cells are substantially aligned with respect to crystal planes of the GaN substrate;
a plurality of channel regions, each having a portion adjacent a sidewall of the plurality of hexagonal cells;
a plurality of gate regions of one or more of the JFETs, each electrically coupled to one or more of the plurality of channel regions; and
a plurality of source regions of one or more of the JFETs electrically coupled to one or more of the plurality of channel regions.

### Claim 2 (depends on 1)

The array of GaN-based vertical JFET of claim 1 wherein the crystal planes are m-planes of the GaN substrate.

### Claim 3 (depends on 1)

The array of GaN-based vertical JFET of claim 1 wherein the GaN substrate comprises an n-type substrate.

### Claim 4 (depends on 3)

The array of GaN-based vertical JFET of claim 3 wherein the plurality of channel regions comprise regrown n-type GaN-based material.

### Claim 5 (depends on 1)

The array of GaN-based vertical JFET of claim 1 wherein the plurality of hexagonal cells comprise portions of a p-type epitaxial layer.

### Claim 6 (depends on 1)

The array of GaN-based vertical JFET of claim 1 wherein the plurality of channel regions include a second portion disposed adjacent a top surface of a hexagonal cell of the plurality of hexagonal cells.

### Claim 7 (depends on 6)

The array of GaN-based vertical JFET of claim 6 wherein the portion of the plurality of channel regions comprises regrown GaN-based material.

### Claim 8

A vertical JFET comprising:
a III-nitride substrate;
a III-nitride epitaxial layer coupled to the III-nitride substrate;
a III-nitride epitaxial structure coupled to the first III-nitride epitaxial layer, wherein the III-nitride epitaxial structure comprises:
a set of hexagonal regrowth pedestals, each having sidewalls and a top surface including a lateral channel layer;
a set of source channel regions, each surrounding one of the set of hexagonal regrowth pedestals, wherein each source channel region comprises a first portion adjacent the sidewalls and a second portion disposed in the lateral channel layer; and
a set of gate regions, each surrounding one of the source regions; and
a drain region electrically coupled to the III-nitride substrate.

### Claim 9 (depends on 8)

The vertical JFET of claim 8 wherein the III-nitride substrate and the III-nitride epitaxial layer are of a first conductivity type and the set of hexagonal regrowth pedestals include a layer of a second conductivity type different from the first conductivity type.

### Claim 10 (depends on 8)

The vertical JFET of claim 8 wherein the first portion of the set of source channel regions is substantially perpendicular to the substrate and the second portion of the set of source channel regions is substantially parallel to the substrate.

### Claim 11 (depends on 8)

The vertical JFET of claim 8 wherein the set of gate regions comprise a regrown gate epitaxial material and a gate contact.

### Claim 12 (depends on 8)

The vertical JFET of claim 8 wherein the second portion of each source channel region is characterized by a length less than 2 μm.

### Claim 13 (depends on 8)

The vertical JFET of claim 8 wherein the second portion of each source channel region is characterized by a thickness less than 200 nm.