# US 2014/0191240 A1 · High Electron Mobility Transistor and Method of Forming the Same

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- Number: US 2014/0191240 A1
- Document ID: US20140191240A1
- Status: Published application
- Kind: A1
- Application number: 13/734,399
- Filed: 2013-01-04
- Published: 2014-07-10
- Earliest claimed: 2013-01-04
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chen-Hao Chiang; Po-Chun Liu; Han-Chin Chiu; Chi-Ming Chen; Chung-Yi Yu
- Web page: https://patentgrep.com/patent/US20140191240A1

## CPC

- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 30/021: {of FETs having insulated gates [IGFET]}
- H10D 30/4732: {using Group III-V semiconductor material}
- H10P 14/3416: {Nitrides}
- H10P 14/40: of conductive or resistive materials
- H10P 30/206: {into Group III-V semiconductors}
- H10P 30/208: {of electrically inactive species}
- H10P 50/283: {by chemical means}
- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- H10D 62/812: {Single quantum well structures}
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10P 14/24: using chemical vapour deposition [CVD]
- H10P 14/3216: {Nitrides}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A High Electron Mobility Transistor (HEMT) includes a first III-V compound layer having a first band gap, and a second III-V compound layer having a second band gap over the first III-V compound layer. The second band gap is smaller than the first band gap. The HEMT further includes a third III-V compound layer having a third band gap over the second III-V compound layer, wherein the third band gap is greater than the first band gap. A gate electrode is formed over the third III-V compound layer. A source region and a drain region are over the third III-V compound layer and on opposite sides of the gate electrode.

## Claims

### Claim 1

A High Electron Mobility Transistor (HEMT) comprising:
a first III-V compound layer;
a second III-V compound layer over the first III-V compound layer;
a third III-V compound layer over the second III-V compound layer, wherein the first III-V compound layer, the second III-V compound layer, and the third III-V compound layer are configured so that a Two-Dimensional Electron Gas (2DEG) is formed in the second III-V compound layer and close to an interface between the second III-V compound layer and the third III-V compound layer;
a gate electrode over the third III-V compound layer; and
a source region and a drain region over the third III-V compound layer and on opposite sides of the gate electrode.

### Claim 2 (depends on 1)

The HEMT of claim 1, wherein the first III-V compound layer has a first band gap, the second III-V compound layer has a second band gap smaller than the first band gap, and wherein the third III-V compound layer has a third band gap greater than the first band gap.

### Claim 3 (depends on 1)

The HEMT of claim 1 further comprising a dielectric passivation layer disposed over the third III-V compound layer, wherein the source region and the drain region penetrate through the dielectric passivation layer to contact the third III-V compound layer.

### Claim 4 (depends on 1)

The HEMT of claim 1 further comprising a gate dielectric comprising a portion disposed between the gate electrode and the third III-V compound layer.

### Claim 5 (depends on 1)

The HEMT of claim 1, wherein the second III-V compound layer comprises indium, and the third III-V compound layer comprises aluminum.

### Claim 6 (depends on 5)

The HEMT of claim 5, wherein the first III-V compound layer comprises gallium nitride (GaN), the second III-V compound layer comprises indium gallium nitride (InGaN), and the third III-V compound layer comprises aluminum gallium nitride (AlGaN).

### Claim 7 (depends on 5)

The HEMT of claim 5, wherein indium in the second III-V compound layer has an atomic percentage greater than about nine percent.

### Claim 8

A High Electron Mobility Transistor (HEMT) comprising:
a gallium nitride (GaN) layer;
an indium gallium nitride (InGaN) layer over and contacting the GaN layer;
an aluminum gallium nitride (AlGaN) layer over and contacting the InGaN layer;
a dielectric passivation layer over the AlGaN layer;
a gate electrode over the AlGaN layer; and
a source region and a drain region over the AlGaN layer, wherein the source region and the drain region are on opposite sides of the gate electrode, and wherein the source region and the drain region penetrate through the dielectric passivation layer to contact the AlGaN layer.

### Claim 9 (depends on 8)

The HEMT of claim 8 further comprising a gate dielectric between the gate electrode and the AlGaN.

### Claim 10 (depends on 9)

The HEMT of claim 9, wherein the gate dielectric further comprises:
a first portion over the dielectric passivation layer, wherein the source region and the drain region penetrate through the first portion of the gate dielectric; and
a second portion in an opening in the dielectric passivation layer, wherein the second portion spaces the gate electrode apart from the AlGaN layer.

### Claim 11 (depends on 9)

The HEMT of claim 9, wherein indium in the InGaN layer has an atomic percentage greater than about 9 percent.

### Claim 12 (depends on 11)

The HEMT of claim 11, wherein the atomic percentage of indium in the InGaN layer is between about 9 percent and about 18 percent.

### Claim 13 (depends on 8)

The HEMT of claim 8 further comprising:
a buffer layer underlying the GaN layer; and
a substrate underlying the buffer layer.

### Claim 14 (depends on 13)

The HEMT of claim 13, wherein the buffer layer comprises:
an aluminum nitride (AlN) layer; and
an additional AlGaN layer over the AlN layer.

### Claim 15

A method of forming a High Electron Mobility Transistor (HEMT), the method comprising:
epitaxially growing a first III-V compound layer having a first band gap;
epitaxially growing a second III-V compound layer having a second band gap smaller than the first band gap over the first III-V compound layer;
epitaxially growing a third III-V compound layer having a third band gap greater than the first band gap over the second III-V compound layer;
forming a gate electrode over the III-V compound layer; and
forming a source region and a drain region over the third III-V compound layer and on opposite sides of the gate electrode.

### Claim 16 (depends on 15)

The method of claim 15, wherein the second III-V compound layer is undoped or unintentionally doped during the step of epitaxially growing the second III-V compound layer.

### Claim 17 (depends on 15)

The method of claim 15 further comprising:
before the step of forming the gate electrode, forming a dielectric passivation layer over and contacting the third III-V compound layer;
patterning the dielectric passivation layer to form an opening, wherein a portion of the third III-V compound layer is exposed through the opening; and
performing the step of forming the gate electrode, wherein the gate electrode extends into the opening.

### Claim 18 (depends on 17)

The method of claim 17 further comprising, after the opening is formed and before the step of forming the gate electrode is performed, forming a gate dielectric layer, wherein the gate dielectric layer comprises a first portion extending into the opening, and a second portion overlapping the dielectric passivation layer.

### Claim 19 (depends on 15)

The method of claim 15, wherein the step of epitaxially growing the first III-V compound layer comprises growing a gallium nitride (GaN) layer, the step of epitaxially growing the second III-V compound layer comprises growing an indium gallium nitride (InGaN) layer, and the step of epitaxially growing the third III-V compound layer comprises growing an aluminum gallium nitride (AlGaN) layer.

### Claim 20 (depends on 15)

The method of claim 15, wherein the second III-V compound layer is grown to contact the first III-V compound layer, and the third III-V compound layer is grown to contact the second III-V compound layer.