# US 2014/0191238 A1 · Thin film transistor array panel > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0191238 A1 - Document ID: US20140191238A1 - Status: Published application - Kind: A1 - Application number: 14/099,977 - Filed: 2013-12-08 - Published: 2014-07-10 - Earliest claimed: 2013-01-04 - Assignees: Samsung Display Co., Ltd. - Applicants: Samsung Display Co., Ltd. - Inventors: Jung Hwan HWANG; Bon-Yong KOO; Soo Jin PARK; Jong-Moon PARK; Yong Hee LEE; Jong-Hyuk LEE; Duc-Han CHO - Web page: https://patentgrep.com/patent/US20140191238A1 ## CPC - H10D 30/6729: {characterised by the electrodes} - H10D 64/258: {characterised by the relative positions of the source or drain electrodes with respect to the gate electrode} - H10D 86/40: characterised by multiple TFTs - H10D 86/441: {Interconnections, e.g. scanning lines} - H10D 86/60: wherein the TFTs are in active matrices - H10H 29/142: {Two-dimensional arrangements, e.g. asymmetric LED layout} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS ## Abstract A thin film transistor array panel includes a gate line elongated in an extension direction and including a gate and dummy gate electrode extended therefrom; and a source electrode, and a single drain member including a drain electrode at a first end thereof and a dummy drain electrode at an opposing second end thereof. The drain electrode faces the source electrode with respect to the gate electrode, and the dummy drain electrode overlaps the dummy gate electrode. The drain and dummy drain electrode respectively include a plurality of first and second regions each having a predetermined width in the extension direction. A second region includes an edge which forms an angle from about 0 degrees to about 90 degrees with the extension direction, and a planar area of at least one of the plurality of second regions is different from that of remaining second regions. ## Claims ### Claim 1 A thin film transistor array panel comprising: a substrate; a gate line elongated in a first direction and comprising a first gate electrode and a second gate electrode and disposed on the substrate; a gate insulating layer on the first gate electrode and the second gate electrode; a semiconductor on the gate insulating layer; and a source electrode and a first drain electrode and a second drain electrode connected to each other disposed on the semiconductor, wherein the first drain electrode faces the source electrode with respect to the first gate electrode, and the second drain electrode is disposed adjacent to the second gate electrode, the drain electrode comprises a plurality of first regions each having a predetermined width in the first direction, and the second drain electrode comprises a plurality of second regions each having a predetermined width in the first direction, at least one of the plurality of second regions comprises an edge which forms an angle from about 0 degrees to about 90 degrees with the first direction, and a planar area of at least one of the plurality of second regions is different from each planar area of remaining second regions of the plurality of second regions. ### Claim 2 (depends on 1) The thin film transistor array panel of claim 1, wherein a first region of the plurality of first regions of the drain electrode comprises an edge which forms an angle from about 0 degrees to about 90 degrees with the first direction, and a planar area of at least one of the plurality of first regions is different from each planar area of remaining first regions of the plurality of first regions. ### Claim 3 (depends on 2) The thin film transistor array panel of claim 2, wherein planar areas of the plurality of first regions and planar areas of the plurality of second regions one of increase or decrease in the first direction away from the source electrode. ### Claim 4 (depends on 3) The thin film transistor array panel of claim 3, wherein the plurality of first regions comprises a first sub-region, a second sub-region and a third sub-region in sequence in the first direction away from the source electrode, the plurality of second regions comprises a fourth sub-region, a fifth sub-region and a sixth sub-region in sequence in the first direction towards the source electrode, the planar area of the first sub-region is the same as the planar area of the sixth sub-region, the planar area of the second sub-region is the same as the planar area of the fifth sub-region, and the planar area of the third sub-region is the same as the planar area of the fourth sub-region. ### Claim 5 (depends on 4) The thin film transistor array panel of claim 4, further comprising: a passivation layer on the source electrode, the first drain electrode and the second drain electrode; and a pixel electrode on the passivation layer and connected to the drain electrode through a contact hole defined in the passivation layer. ### Claim 6 (depends on 5) The thin film transistor array panel of claim 5, further comprising a common electrode overlapping the pixel electrode; and an insulating layer between the common electrode and the pixel electrode. ### Claim 7 (depends on 6) The thin film transistor array panel of claim 6, wherein one of the pixel electrode and the common electrode comprises a plurality of branch electrodes, and the other of the pixel electrode and the common electrode is plate-shaped. ### Claim 8 (depends on 1) The thin film transistor array panel of claim 1, wherein planar areas of the plurality of first regions and planar areas of the plurality of second regions one of increase or decrease in the first direction away from the source electrode. ### Claim 9 (depends on 8) The thin film transistor array panel of claim 8, wherein the plurality of first regions comprises a first sub-region, a second sub-region and a third sub-region in sequence in the first direction away from the source electrode, the plurality of second regions comprises a fourth sub-region, a fifth sub-region and a sixth sub-region in sequence in the first direction towards the source electrode, the planar area of the first sub-region is the same as the planar area of the sixth sub-region, the planar area of the second sub-region is the same as the planar area of the fifth sub-region, and the planar area of the third sub-region is the same as the planar area of the fourth sub-region. ### Claim 10 (depends on 9) The thin film transistor array panel of claim 9, further comprising: a passivation layer on the source electrode, the first drain electrode and the second drain electrode; and a pixel electrode on the passivation layer and connected to the drain electrode through a contact hole defined in the passivation layer. ### Claim 11 (depends on 10) The thin film transistor array panel of claim 10, further comprising a common electrode overlapping the pixel electrode; and an insulating layer between the common electrode and the pixel electrode. ### Claim 12 (depends on 11) The thin film transistor array panel of claim 11, wherein one of the pixel electrode and the common electrode comprises a plurality of branch electrodes, and the other the pixel electrode and the common electrode is plate-shaped. ### Claim 13 (depends on 1) The thin film transistor array panel of claim 1, wherein the plurality of first regions comprises a first sub-region, a second sub-region and a third sub-region in sequence in the first direction away from the source electrode, the plurality of second regions comprises a fourth sub-region, a fifth sub-region and a sixth sub-region in sequence in the first direction towards the source electrode, a planar area of the first sub-region is the same as a planar area of the sixth sub-region, a planar area of the second sub-region is the same as a planar area of the fifth sub-region, and a planar area of the third sub-region is the same as a planar area of the fourth sub-region. ### Claim 14 (depends on 13) The thin film transistor array panel of claim 13, further comprising: a passivation layer on the source electrode, the first drain electrode and the second drain electrode; and a pixel electrode on the passivation layer and connected to the drain electrode through a contact hole defined in the passivation layer. ### Claim 15 (depends on 14) The thin film transistor array panel of claim 14, further comprising a common electrode overlapping the pixel electrode; and an insulating layer between the common electrode and the pixel electrode. ### Claim 16 (depends on 15) The thin film transistor array panel of claim 15, wherein one of the pixel electrode and the common electrode comprises a plurality of branch electrodes, and the other the pixel electrode and the common electrode is plate-shaped. ### Claim 17 A thin film transistor array panel comprising: a substrate; a gate line elongated in a first direction, and comprising a first gate electrode and a second gate electrode extended therefrom, on the substrate; a gate insulating layer on the first gate electrode and the second gate electrode; a semiconductor on the gate insulating layer; and a source electrode and a first drain electrode and a drain electrode connected to each other disposed on the semiconductor, wherein the first drain electrode faces the source electrode with respect to the first gate electrode, and the second drain electrode is disposed adjacent to the second gate electrode, the first drain electrode comprises a plurality of first regions each having a predetermined width in the first direction, and the second drain electrode comprises a plurality of third regions each having a predetermined width in the first direction, and a planar area of at least one of the plurality of third regions of the second drain electrode is different from each planar area of remaining third regions of the plurality of third regions. ### Claim 18 (depends on 17) The thin film transistor array panel of claim 17, wherein a first region of the plurality of first regions of the drain electrode comprises an edge which forms an angle from about 0 degrees to about 90 degrees with the first direction, and a planar area of at least one of the plurality of first regions is different from each planar area of remaining first regions of the plurality of first regions. ### Claim 19 (depends on 18) The thin film transistor array panel of claim 18, wherein planar areas of the plurality of first regions and planar areas of the plurality of third regions one of increase and decrease in the first direction away from the source electrode. ### Claim 20 (depends on 17) The thin film transistor array panel of claim 17, wherein planar areas of the plurality of first regions and planar areas of the plurality of third regions one of increase and decrease in the first direction away from the source electrode.