# US 2014/0191237 A1 · Crystalline thin-film transistor

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- Number: US 2014/0191237 A1
- Document ID: US20140191237A1
- Status: Published application
- Kind: A1
- Application number: 13/967,128
- Filed: 2013-08-14
- Published: 2014-07-10
- Earliest claimed: 2013-01-08
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: BAHMAN HEKMATSHOARTABARI; NING LI; DEVENDRA K. SADANA; DAVOOD SHAHRJERDI
- Web page: https://patentgrep.com/patent/US20140191237A1

## CPC

- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/0323: {comprising monocrystalline silicon}
- H10D 30/67: Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)}
- H10D 30/6731: {Top-gate only TFTs}
- H10D 30/6744: {Monocrystalline silicon}
- H10D 30/6745: {Polycrystalline or microcrystalline silicon}
- H10H 20/062: {Light-emitting semiconductor devices having field effect type light-emitting regions, e.g. light-emitting High-Electron Mobility Transistors}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS

## Abstract

A method for forming a thin film transistor includes joining a crystalline substrate to an insulating substrate. A doped layer is deposited on the crystalline substrate, and the doped layer is patterned to form source and drain regions. The crystalline substrate is patterned to form an active area such that a conductive channel is formed in the crystalline substrate between the source and drain regions. A gate stack is formed between the source and drain regions, and contacts are formed to the source and drain regions and the gate stack through a passivation layer.

## Claims

### Claim 1

A thin film transistor, comprising:
a crystalline substrate wafer bonded to an insulating substrate and patterned to form an active area such that a conductive channel is formed in the crystalline substrate;
epitaxial crystalline source and drain regions formed on an upper surface of the crystalline substrate on opposing sides of the conductive channel;
a gate stack formed between the source and drain regions; and
contacts coupled to the source and drain regions and the gate stack and formed through a passivation layer.

### Claim 2 (depends on 1)

The thin film transistor as recited in claim 1, wherein the insulating substrate includes glass or plastic.

### Claim 3 (depends on 1)

The thin film transistor as recited in claim 1, wherein the conductive channel includes a width to length ratio of less than 25.

### Claim 4 (depends on 1)

The thin film transistor as recited in claim 1, wherein the conductive channel includes a width to length ratio of less than 5.

### Claim 5 (depends on 1)

The thin film transistor as recited in claim 1, wherein the insulating substrate includes a handle substrate employed during wafer bonding.

### Claim 6 (depends on 1)

The thin film transistor as recited in claim 1, wherein the thin film transistor is configured to drive an organic light emitting diode pixel.

### Claim 7 (depends on 1)

The thin film transistor as recited in claim 1, wherein the gate stack includes a high dielectric constant (high-K) gate dielectric and a metal gate conductor.

### Claim 8 (depends on 1)

The thin film transistor as recited in claim 1, wherein the crystalline substrate is monocrystalline.

### Claim 9 (depends on 1)

The thin film transistor as recited in claim 1, wherein the crystalline substrate.