# US 2014/0191234 A1 · Three Dimensional Stacked Structure for Chips > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0191234 A1 - Document ID: US20140191234A1 - Status: Published application - Kind: A1 - Application number: 14/147,293 - Filed: 2014-01-03 - Published: 2014-07-10 - Earliest claimed: 2013-01-04 - Inventors: Tsai-Yu Huang; Yi-Feng Huang - Web page: https://patentgrep.com/patent/US20140191234A1 ## CPC - H10W 20/42: Vias, e.g. via plugs - H10P 74/273: {Interconnections for measuring or testing, e.g. probe pads} - H10W 90/00: Package configurations - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10W 72/01: {Manufacture or treatment} - H10W 90/284: {characterised by structural arrangements for measuring or testing} - H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips} - H10W 90/722: {between stacked chips} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A 3-D chip stacked structure is disclosed. Each chip layer is provided with plural single-layered conductive members where among the same chip layer the two adjacent conductive members are structurally formed in minor symmetric way with each other along a chip longitudinal direction and the arrangements of the single-layered conductive members of the two adjacent chip layers are shifted by a test pad distance. The single-layered conductive members of the two adjacent chip layers are communicated through a vertical TSV (through silicon via). Therefore, a selection signal or an enabling signal might be transferred through this specific metal layer and related TSV to reach targeting chip layer and targeting circuit. ## Claims ### Claim 1 A three dimensional chips stacked structure, comprising plural chips layers, each of said plural chips layers having plural single-layered conductive members formed thereon, each of said plural single-layered conductive members having a test pad formed thereon, wherein two adjacent said single-layered conductive members for said each of said plural chips layers are structurally formed in minor symmetry with each other along a chip longitudinal direction and an arrangement of said plural single-layered conductive members of two adjacent chip layers are shifted by a predetermined distance, and said plural single-layered conductive members of said two adjacent chip layers communicated through a vertical TSV. ### Claim 2 (depends on 1) The structure of claim 1, wherein said each of said plural single-layered conductive members includes a pad branch and a non-pad branch, wherein said test pad is configured on said pad branch. ### Claim 3 (depends on 2) The structure of claim 2, wherein for said two adjacent chip layers, at least one said single-layered conductive members of top chip layer extends from said non-pad branch vertically downward to corresponding single-layered conductive member of underlying chip layer by said TSV. ### Claim 4 (depends on 2) The structure of claim 2, wherein between said pad branch and said non-pad branch has an included angle. ### Claim 5 (depends on 1) The structure of claim 1, wherein said plural single-layered conductive members is L-shaped. ### Claim 6 (depends on 1) The structure of claim 1, wherein a material of said plural single-layered conductive members is copper. ### Claim 7 (depends on 1) The structure of claim 1, wherein said each of plural single-layered conductive members is connected to a corresponding distinct circuit. ### Claim 8 (depends on 7) The structure of claim 7, wherein said corresponding distinct circuit of any one of said plural chips layers is applied to a relatively high voltage, others corresponding distinct circuit of said plural chips layers is applied to a relatively low voltage. ### Claim 9 (depends on 1) The structure of claim 1, wherein said corresponding distinct circuit includes an input terminal connected to a drain electrode of a first N-type metal oxide semiconductor field effect transistors (NMOS), a output terminal connected to a lock control circuit, a gate electrode of said first NMOS connected to a reset signal source, a source electrode of said first NMOS connected to ground. ### Claim 10 (depends on 9) The structure of claim 9, wherein said lock control circuit includes a first inverter, a second converter, a second NMOS and a third NMOS. ### Claim 11 (depends on 10) The structure of claim 10, wherein said output terminal is connected to an input terminal of said first inverter and a source electrode of said second NMOS, and an output terminal of said first inverter is connected to an input terminal of said second inverter and a gate electrode of said second NMOS. ### Claim 12 (depends on 11) The structure of claim 11, wherein an output terminal of said second inverter is connected to a gate electrode of said third NMOS, a drain electrode of said second NMOS is connected to a source electrode of said third NMOS, and a drain electrode of said third NMOS is connected to ground. ### Claim 13 (depends on 12) The structure of claim 12, wherein a connecting wire is used to connect to said source electrode of said third NMOS for all lock control circuits. ### Claim 14 (depends on 1) The structure of claim 1, wherein one of said single-layered conductive members on far left side for each chip layer is connected to a select circuit. ### Claim 15 (depends on 1) The structure of claim 1, wherein one of said single-layered conductive members on far right side for each chip layer is connected to a select circuit. ### Claim 16 (depends on 1) The structure of claim 1, wherein said test pad is square aluminum pad.