# US 2014/0191232 A1 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0191232 A1 - Document ID: US20140191232A1 - Status: Published application - Kind: A1 - Application number: 14/207,750 - Filed: 2014-03-13 - Published: 2014-07-10 - Earliest claimed: 2009-11-27 - Assignees: Semiconductor Energy Laboratory Co., Ltd. - Applicants: Semiconductor Energy Laboratory Co., Ltd. - Inventors: Shunpei Yamazaki; Hiromichi Godo; Daisuke Kawae - Web page: https://patentgrep.com/patent/US20140191232A1 ## CPC - H10D 30/6756: {Amorphous oxide semiconductors} - H10D 30/6729: {characterised by the electrodes} - H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes} - H10D 30/6739: {Conductor-insulator-semiconductor electrodes} - H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate} - H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)} - H10D 99/00: Subject matter not provided for in other groups of this subclass - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract An intrinsic or substantially intrinsic semiconductor, which has been subjected to a step of dehydration or dehydrogenation and a step of adding oxygen so that the carrier concentration is less than 1×1012/cm3 is used for an oxide semiconductor layer of an insulated gate transistor, in which a channel region is formed. The length of the channel formed in the oxide semiconductor layer is set to 0.2 μm to 3.0 μm inclusive and the thicknesses of the oxide semiconductor layer and the gate insulating layer are set to 15 nm to 30 nm inclusive and 20 nm to 50 nm inclusive, respectively, or 15 nm to 100 nm inclusive and 10 nm to 20 nm inclusive, respectively. Consequently, a short-channel effect can be suppressed, and the amount of change in threshold voltage can be less than 0.5 V in the range of the above channel lengths. ## Claims ### Claim 1 (canceled) ### Claim 2 A semiconductor device comprising: a gate electrode layer; a gate insulating layer adjacent to the gate electrode layer; and an oxide semiconductor layer adjacent to the gate electrode layer with the gate insulating layer therebetween, wherein a carrier concentration of the oxide semiconductor layer is less than 1×1012/cm3, wherein a length of a channel formed in the oxide semiconductor layer is 3.0 μm or less, wherein a thickness of the oxide semiconductor layer is 15 nm to 30 nm, wherein a thickness of the gate insulating layer is 20 nm to 50 nm, and wherein the oxide semiconductor layer comprises indium and zinc. ### Claim 3 (depends on 2) The semiconductor device according to claim 2, wherein the length of the channel formed in the oxide semiconductor layer is 0.2 μm or more. ### Claim 4 (depends on 2) The semiconductor device according to claim 2, wherein the gate electrode layer comprises a film containing a metal element selected from aluminum, copper, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, and scandium as its main component; an alloy film; or a stack of any of these films. ### Claim 5 (depends on 2) The semiconductor device according to claim 2, wherein the gate insulating layer comprises a single-layer film or a laminate film of any of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, and tantalum oxide. ### Claim 6 (depends on 2) An electronic device comprising the semiconductor device according to claim 2. ### Claim 7 A semiconductor device comprising a transistor, the transistor comprising: a gate electrode layer; a gate insulating layer adjacent to the gate electrode layer; and an oxide semiconductor layer adjacent to the gate electrode layer with the gate insulating layer therebetween, wherein a length of a channel formed in the oxide semiconductor layer is 3.0 μm or less, wherein a thickness of the oxide semiconductor layer is 15 nm to 30 nm, wherein a thickness of the gate insulating layer is 20 nm to 50 nm, wherein the oxide semiconductor layer includes a region in which a concentration of hydrogen is 5×1019/cm3 or less, wherein an off current per micrometer in a channel width is 100 aA/μm or less when a drain voltage of 1 V to 10 V is applied, and wherein the oxide semiconductor layer comprises indium and zinc. ### Claim 8 (depends on 7) The semiconductor device according to claim 7, wherein the length of the channel formed in the oxide semiconductor layer is 0.2 μm or more. ### Claim 9 (depends on 7) The semiconductor device according to claim 7, wherein the gate electrode layer comprises a film containing a metal element selected from aluminum, copper, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, and scandium as its main component; an alloy film; or a stack of any of these films. ### Claim 10 (depends on 7) The semiconductor device according to claim 7, wherein the gate insulating layer comprises a single-layer film or a laminate film of any of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, and tantalum oxide. ### Claim 11 (depends on 7) An electronic device comprising the semiconductor device according to claim 7. ### Claim 12 A semiconductor device comprising: an oxide semiconductor layer; a source electrode layer and a drain electrode layer over the oxide semiconductor layer; a gate insulating layer over the oxide semiconductor layer, the source electrode layer, and the drain electrode layer; and a gate electrode layer over the gate insulating layer; wherein the gate electrode layer overlaps the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, wherein a carrier concentration of the oxide semiconductor layer is less than 1×1012/cm3, wherein a length of a channel formed in the oxide semiconductor layer is 3.0 μm or less, wherein a thickness of the oxide semiconductor layer is 15 nm to 30 nm, wherein a thickness of the gate insulating layer is 20 nm to 50 nm, and wherein the oxide semiconductor layer comprises indium and zinc. ### Claim 13 (depends on 2) The semiconductor device according to claim 2, further comprising an insulating layer, wherein the oxide semiconductor layer is provided over the insulating layer. ### Claim 14 (depends on 12) The semiconductor device according to claim 12, wherein the length of the channel formed in the oxide semiconductor layer is 0.2 μm or more. ### Claim 15 (depends on 12) The semiconductor device according to claim 12, wherein the gate electrode layer comprises a film containing a metal element selected from aluminum, copper, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, and scandium as its main component; an alloy film; or a stack of any of these films. ### Claim 16 (depends on 12) The semiconductor device according to claim 12, wherein the gate insulating layer comprises a single-layer film or a laminate film of any of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, and tantalum oxide. ### Claim 17 (depends on 12) An electronic device comprising the semiconductor device according to claim 12.