# US 2014/0191228 A1 · Thin film transistor, method of fabricating the same, and display apparatus having the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0191228 A1 - Document ID: US20140191228A1 - Status: Published application - Kind: A1 - Application number: 13/893,817 - Filed: 2013-05-14 - Published: 2014-07-10 - Earliest claimed: 2013-01-07 - Assignees: Samsung Display Co., Ltd. - Applicants: Samsung Display Co., Ltd. - Inventors: SEOHONG JUNG; Sun Hee Lee; Seung-Hwan Cho; Myounggeun Cha; Yoonho Khang; Youngki Shin - Web page: https://patentgrep.com/patent/US20140191228A1 ## CPC - H10D 30/6715: {characterised by the doping profiles, e.g. having lightly-doped source or drain extensions} - H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A thin film transistor includes a semiconductor layer disposed on a base substrate and including an oxide semiconductor material, a source electrode and a drain electrode, which respectively extend from opposing ends of the semiconductor layer, a plurality of low carrier concentration areas respectively disposed between the source electrode and the semiconductor layer and between the drain electrode and the semiconductor layer, a gate insulating layer disposed on the semiconductor layer, and a gate electrode disposed on the gate insulating layer. ## Claims ### Claim 1 A thin film transistor comprising: a semiconductor layer disposed on a base substrate and including an oxide semiconductor material; a source electrode and a drain electrode, which respectively extend from opposing ends of the semiconductor layer; a plurality of low carrier concentration areas respectively disposed between the source electrode and the semiconductor layer and between the drain electrode and the semiconductor layer; a gate insulating layer disposed on the semiconductor layer; and a gate electrode disposed on the gate insulating layer. ### Claim 2 (depends on 1) The thin film transistor of claim 1, wherein the source electrode, the drain electrode, and the low carrier concentration areas comprise a same material as a material of the semiconductor layer, and wherein the oxide semiconductor material includes at least one of zinc, indium, gallium, tin, or a mixture thereof. ### Claim 3 (depends on 2) The thin film transistor of claim 2, wherein each of the low carrier concentration areas has a width in a range of from about 0.5 μm to about 2 μm. ### Claim 4 (depends on 3) The thin film transistor of claim 3, wherein a carrier concentration of the low carrier concentration areas is higher than a carrier concentration of the semiconductor layer and lower than a carrier concentration of the source and drain electrodes. ### Claim 5 (depends on 4) The thin film transistor of claim 4, wherein the carrier concentration of the low carrier concentration areas is in a range of from about 1017/cm3 to about 1018/cm3, the carrier concentration of the semiconductor layer is no greater than about 1016/cm3, and the carrier concentration of the source and the drain electrodes is in a range of from about 1018/cm3 to about 1019/cm3. ### Claim 6 A method of manufacturing a thin film transistor, comprising: forming an oxide semiconductor pattern including an oxide semiconductor material on a base substrate; forming a gate insulating layer covering the oxide semiconductor pattern; forming a gate electrode on the gate insulating layer and overlapping with the oxide semiconductor pattern; performing a first plasma treatment on first areas of the oxide semiconductor pattern which include opposing ends of the oxide semiconductor pattern to form a source electrode and a drain electrode; and performing a second plasma treatment on second areas of the oxide semiconductor pattern, which are not overlapped with the gate electrode between the source electrode and the drain electrode, to form a plurality of low carrier concentration areas. ### Claim 7 (depends on 6) The method of claim 6, further comprising: performing a first patterning process on the gate insulating layer exposing the first areas after the gate electrode is formed; and performing a second patterning process on the gate insulating layer exposing the second areas after the source and drain electrodes are formed. ### Claim 8 (depends on 7) The method of claim 7, wherein the forming of the gate electrode, the exposing of the first areas, and the forming of the source and drain electrodes are performed using a first photoresist pattern, and wherein the exposing of the second areas and the forming of the low carrier concentration areas are performed using a second photoresist pattern. ### Claim 9 (depends on 7) The method of claim 7, wherein the forming of the gate electrode, the exposing of the first areas, the forming of the source and drain electrodes, the exposing of the second areas, and the forming of the low carrier concentration areas are performed using a photoresist pattern having a thickness at a center portion thereof thicker than a thickness at opposing end portions thereof. ### Claim 10 (depends on 7) The method of claim 7, wherein each of the low carrier concentration areas has a width in a range of from about 0.5 μm to about 2 μm. ### Claim 11 (depends on 10) The method of claim 10, wherein the low carrier concentration areas have a carrier concentration higher than a carrier concentration of the semiconductor layer and lower than a carrier concentration of the source and drain electrodes. ### Claim 12 A display apparatus comprising: a base substrate; a thin film transistor disposed on the base substrate; and a display device that makes contact with the thin film transistor, wherein the thin film transistor comprises: a semiconductor layer disposed on the base substrate and including an oxide semiconductor material, a source electrode and a drain electrode, which respectively extend from opposing ends of the semiconductor layer,and a plurality of low carrier concentration areas respectively disposed between the source electrode and the semiconductor layer and between the drain electrode and the semiconductor layer; a gate insulating layer disposed on the semiconductor layer; and a gate electrode disposed on the gate insulating layer. ### Claim 13 (depends on 12) The display apparatus of claim 12, wherein the display device comprises: a first electrode making contact with the drain electrode; a second electrode facing the first electrode; and an optical layer interposed between the first electrode and the second electrode. ### Claim 14 (depends on 13) The display apparatus of claim 13, wherein the source electrode, the drain electrode, and the low carrier concentration areas comprise a same material as a material of the semiconductor layer, and wherein the oxide semiconductor material comprises at least one of zinc, indium, gallium, tin, or a mixture thereof. ### Claim 15 (depends on 14) The display apparatus of claim 14, wherein each of the low carrier concentration areas has a carrier concentration higher than a carrier concentration of the semiconductor layer and lower than a carrier concentration of the source and drain electrodes. ### Claim 16 (depends on 15) The display apparatus of claim 15, wherein each of the low carrier concentration areas has a width from about 0.5 μm to about 2 μm. ### Claim 17 (depends on 13) The display apparatus of claim 13, further comprising: a protection layer that covers the thin film transistor and includes a first contact hole exposing a portion of the source electrode and a second contact hole exposing a portion of the drain electrode; and a data line disposed on the protection layer making contact with the source electrode through the first contact hole, wherein the first electrode makes contact with the drain electrode through the second contact hole. ### Claim 18 (depends on 13) The display apparatus of claim 13, further comprising a data line extending from the source electrode, wherein the first electrode extends from the drain electrode. ### Claim 19 (depends on 18) The display apparatus of claim 18, further comprising a protection layer covering the thin film transistor and exposing the first electrode. ### Claim 20 (depends on 12) The display apparatus of claim 12, further comprising an insulating layer interposed between the base substrate and the thin film transistor. ### Claim 21 (depends on 17) The display apparatus of claim 17, wherein the protection layer includes an inorganic protection layer and an organic protection layer disposed on the inorganic protection layer, wherein the inorganic protection layer includes at least one of silicon oxide or silicon nitride, and wherein the organic protection layer includes one of acryl, polyimide, polyamide, or benzocyclobutene. ### Claim 22 (depends on 19) The display apparatus of claim 19, wherein the protection layer includes an inorganic protection layer and an organic protection layer disposed on the inorganic protection layer, wherein the inorganic protection layer includes at least one of silicon oxide or silicon nitride, and wherein the organic protection layer includes one of acryl, polyimide, polyamide, or benzocyclobutene. ### Claim 23 (depends on 17) The display apparatus of claim 17, wherein the first electrode is disposed on a same layer as the data line and includes a same material as a material of the data line. ### Claim 24 A display apparatus comprising: a base substrate; a thin film transistor disposed on the base substrate; a display device that makes contact with the thin film transistor; an insulating layer disposed between the base substrate and the thin film transistor; wherein the thin film transistor comprises: a semiconductor layer disposed on the insulating layer and including an oxide semiconductor material, a source electrode and a drain electrode, which respectively extend from opposing ends of the semiconductor layer, a plurality of low carrier concentration areas respectively disposed between the source electrode and the semiconductor layer and between the drain electrode and the semiconductor layer, a data line connected to the source electrode, and a first electrode connected to the drain electrode, wherein one end of the source electrode extends to and is connected to the data line and one end of the drain electrode extends to and is connected to the first electrode of the display device and wherein the source electrode, the drain electrode, the low carrier concentrations areas, the semiconductor layer, the data line and the first electrode each include a same material as one another and are each disposed on a same layer as one another; a gate insulating layer disposed on the semiconductor layer; a gate electrode disposed on the gate insulating layer and overlapping with the semiconductor layer; and a protection layer disposed on the thin film transistor, and wherein the protection layer exposes a portion of the first electrode. ### Claim 25 (depends on 24) The display apparatus of claim 24, wherein the protection layer is in direct physical contact with the source electrode, the drain electrode and the gate electrode.