# US 2014/0191198 A1 · Graphene electronic devices and methods of manufacturing the same

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- Number: US 2014/0191198 A1
- Document ID: US20140191198A1
- Status: Published application
- Kind: A1
- Application number: 13/975,680
- Filed: 2013-08-26
- Published: 2014-07-10
- Earliest claimed: 2013-01-08
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Yong-sung KIM; Chang-seung LEE; Joo-ho LEE
- Web page: https://patentgrep.com/patent/US20140191198A1

## CPC

- H10D 30/021: {of FETs having insulated gates [IGFET]}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10B 41/30: characterised by the memory core region
- H10B 51/30: characterised by the memory core region
- H10D 30/01: Manufacture or treatment
- H10D 30/47: having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
- H10D 30/681: {having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688)}
- H10D 30/6892: {having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate}
- H10D 30/701: {IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs}
- H10D 62/8303: {Diamond}
- H10D 62/882: {Graphene}
- H10D 64/033: {comprising ferroelectric layers}
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10P 72/74: {using temporarily an auxiliary support}
- H10D 64/258: {characterised by the relative positions of the source or drain electrodes with respect to the gate electrode}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10P 72/744: {Details of chemical or physical process used for separating the auxiliary support from a device or a wafer}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A graphene electronic device includes: a first conductive layer and a semiconductor layer on a first region of an intermediate layer; a second conductive layer on a second region of the intermediate layer; a graphene layer on the intermediate layer, the semiconductor layer, and the second conductive layer; and a first gate structure and a second gate structure on the graphene layer.

## Claims

### Claim 1

A graphene electronic device comprising:
a first conductive layer and a semiconductor layer on a first region of an intermediate layer;
a second conductive layer on a second region of the intermediate layer;
a graphene layer on the intermediate layer, the semiconductor layer, and the second conductive layer; and
a first gate structure and a second gate structure on the graphene layer.

### Claim 2 (depends on 1)

The device of claim 1, wherein the first gate structure corresponds to the first region of the intermediate layer.

### Claim 3 (depends on 1)

The device of claim 1, wherein the second gate structure corresponds to a space between the first region and the second region of the intermediate layer.

### Claim 4 (depends on 1)

The device of claim 1, wherein the intermediate layer is on a support structure.

### Claim 5 (depends on 1)

The device of claim 1, wherein the first gate structure includes a gate insulating layer and a first gate.

### Claim 6 (depends on 5)

The device of claim 5, wherein the second gate structure includes the gate insulating layer and a second gate.

### Claim 7 (depends on 1)

The device of claim 1, wherein the first gate structure includes a first ferroelectric layer and a first gate.

### Claim 8 (depends on 7)

The device of claim 7, wherein the second gate structure includes a second ferroelectric layer and a second gate.

### Claim 9 (depends on 1)

The device of claim 1, wherein the first gate structure includes a first tunneling oxide layer, a first floating gate, a first blocking oxide layer, and a first gate.

### Claim 10 (depends on 9)

The device of claim 9, wherein the second gate structure includes a second tunneling oxide layer, a second floating gate, a second blocking oxide layer, and a second gate.

### Claim 11

A method of forming a graphene electronic device, the method comprising:
forming a semiconductor layer, a first conductive layer, and a second conductive layer on a substrate;
forming an intermediate layer on the substrate, the semiconductor layer, the first conductive layer, and the second conductive layer;
forming a graphene layer on the intermediate layer, the semiconductor layer, and the second conductive layer; and
forming a first gate structure and a second gate structure on the graphene layer.

### Claim 12 (depends on 11)

The method of claim 11, further comprising:
forming a support structure on the intermediate layer.

### Claim 13 (depends on 11)

The method of claim 11, further comprising:
removing the substrate.

### Claim 14 (depends on 13)

The method of claim 13, wherein the substrate includes silicon and a silicon oxide layer, and wherein the substrate is removed by etching the silicon oxide layer.

### Claim 15 (depends on 13)

The device of claim 13, wherein the substrate includes a transparent substrate, and wherein the substrate is removed by a laser lift-off process.

### Claim 16 (depends on 11)

The device of claim 11, wherein the graphene layer is formed on a catalyst layer by a pyrolisis method or a chemical vapor deposition (CVD) method.

### Claim 17

A graphene electronic device comprising:
a graphene transistor having a channel including a graphene layer and an electrode including a semiconductor layer; and
a graphene tunable diode having a diode region including the graphene layer and the semiconductor layer.

### Claim 18 (depends on 17)

The device of claim 17, wherein the graphene transistor comprises:
a first conductive layer and the semiconductor layer on a first region of an intermediate layer;
a second conductive layer on a second region of the intermediate layer;
the graphene layer on the intermediate layer, the semiconductor layer, and the second conductive layer; and
a gate structure on the graphene layer.

### Claim 19 (depends on 18)

The device of claim 18, wherein the gate structure includes a tunneling oxide layer, a floating gate, a blocking oxide layer, and a gate.

### Claim 20 (depends on 18)

The device of claim 18, wherein the gate structure includes a ferroelectric layer and a gate.

### Claim 21 (depends on 17)

The device of claim 17, wherein the graphene tunable diode comprises:
the semiconductor layer on a first region of an intermediate layer;
the graphene layer on the intermediate layer and the semiconductor layer; and
a gate structure on the graphene layer corresponding to the first region of the intermediate layer.

### Claim 22 (depends on 21)

The device of claim 21, wherein the gate structure includes a ferroelectric layer and a gate.

### Claim 23 (depends on 21)

The device of claim 21, wherein the gate structure includes a tunneling oxide layer, a floating gate, a blocking oxide layer, and a gate.

### Claim 24 (depends on 17)

The device of claim 17, further comprising:
a first gate structure corresponding to the graphene transistor; and
a second gate structure corresponding to the graphene tunable diode.