# US 2014/0191179 A1 · Vertical bipolar transistor

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- Number: US 2014/0191179 A1
- Document ID: US20140191179A1
- Status: Published application
- Kind: A1
- Application number: 14/150,596
- Filed: 2014-01-08
- Published: 2014-07-10
- Earliest claimed: 2013-01-08
- Assignees: STMicroelectronics (Rousset) SAS
- Applicants: STMicroelectronics (Rousset) SAS
- Inventors: Philippe Boivin; Francesco La Rosa; Julien Delalleau
- Web page: https://patentgrep.com/patent/US20140191179A1

## CPC

- H10B 63/32: {of the bipolar type}
- H10B 61/20: {comprising components having three or more electrodes, e.g. transistors}
- H10D 10/051: {of vertical BJTs (of heterojunction BJTs H10D10/021; of Schottky BJTs H10D10/031; of thin film BJTs H10D10/041)}
- H10D 10/40: Vertical BJTs {(Vertical Heterojunction BJTs H10D10/821)}
- H10N 70/011: {Manufacture or treatment of multistable switching devices}
- H10N 70/20: Multistable switching devices, e.g. memristors
- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- H10D 62/137: {Collector regions of BJTs}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

The disclosure relates to an integrated circuit comprising a transistor comprising first and second conduction terminals and a control terminal. The integrated circuit further comprises a stack of a first dielectric layer, a conductive layer, and a second dielectric layer, the first conduction terminal comprising a first semiconductor region formed in the first dielectric layer, the control terminal comprising a second semiconductor region formed in the conductive layer, and the second conduction terminal comprising a third semiconductor region formed in the second dielectric layer.

## Claims

### Claim 1

An integrated circuit, comprising:
a transistor having:
first and second conduction terminals;
a control terminal;
a stack of a first dielectric layer, a conductive layer, and a second dielectric layer,
the first conduction terminal of the transistor including a first semiconductor region of a first conductivity type formed in the first dielectric layer,
the control terminal of the transistor including a second semiconductor region of a second conductivity type formed in the conductive layer, and
the second conduction terminal of the transistor including a third semiconductor region of the first conductivity type formed in the second dielectric layer.

### Claim 2 (depends on 1)

An integrated circuit according to claim 1 wherein the conductive layer is a semiconductor material including dopants of the second conductivity type, and the second region including a diffusion profile wherein lateral edges are thicker than a middle.

### Claim 3 (depends on 1)

An integrated circuit according to claim 1 wherein the stack of layers is formed on a surface of a semiconductor substrate, the substrate including a well having dopants of the first conductivity type underlying at least the first region.

### Claim 4 (depends on 3)

An integrated circuit according to claim 3 wherein the first region includes a diffusion profile wherein a middle is thicker than lateral edges of the first region.

### Claim 5

A memory cell, comprising:
a data storage element;
a transistor coupled to the data storage element, the transistor having:
a first dielectric layer;
a conductive layer;
a second dielectric layer;
a first conduction terminal including a first semiconductor region of a first conductivity type formed in the first dielectric layer;
a control terminal including a second semiconductor region of a second conductivity type formed in the conductive layer; and
a second conduction terminal including a third semiconductor region of the first conductivity type formed in the second dielectric layer.

### Claim 6 (depends on 5)

A memory cell according to claim 5 wherein the data storage element is a resistive storage element including a first metal electrode, a resistive material, and a second metal electrode, and wherein one of the electrodes is coupled to the first conduction terminal of the transistor.

### Claim 7

A device, comprising:
an array of memory cells the memory cells being arranged in at least one row, each memory cell including:
a data storage element;
a transistor coupled to the data storage element, the transistor having:
a first dielectric layer;
a conductive layer;
a second dielectric layer;
a first conduction terminal including a first semiconductor region of a first conductivity type formed in the first dielectric layer;
a control terminal including a second semiconductor region of a second conductivity type formed in the conductive layer; and
a second conduction terminal including a third semiconductor region of the first conductivity type formed in the second dielectric layer;
the conductive layer extends between and is shared with each transistor in a row and is coupled to the control terminals of all memory cells of the row.

### Claim 8 (depends on 7)

The device of claim 7 wherein the conductive layer is a semiconductor material including dopants of the second conductivity type, and the second region including a diffusion profile wherein lateral edges are thicker than a middle.

### Claim 9

A method, comprising:
forming a transistor that includes first and second conduction terminals and a control terminal, the forming of the transistor including:
forming a stack of a first dielectric layer, a conductive layer, and a second dielectric layer;
forming the first conduction terminal as a first semiconductor region of a first conductivity type in the first dielectric layer;
forming the control terminal as a second semiconductor region of a second conductivity type in the conductive layer; and
forming the second conduction terminal as a third semiconductor region of the first conductivity type in the second dielectric layer.

### Claim 10 (depends on 9)

A method according to claim 9, further comprising:
etching a hole through at least one of the layers; and
depositing a semiconductor material in the hole.

### Claim 11 (depends on 9)

A method according to claim 9 wherein the conductive layer is a semiconductor material including dopants of the second conductivity type, and the forming of the transistor includes diffusing dopants from the conductive layer to form the second region.

### Claim 12 (depends on 10)

A method according to claim 10, further comprising:
forming, in a semiconductor substrate, a well including dopants of the first conductivity type, the well underlying at least the first region; and
diffusing dopants of the first conductivity type from the well into the semiconductor material in the hole to form the first region.

### Claim 13 (depends on 10)

A method according to claim 10, further comprising:
implanting dopants of the first conductivity type into the top surface of the semiconductor material; and
diffusing the dopants into the semiconductor material in the hole to form the third region.