# US 2014/0191178 A1 · Method of fabricating a vertical mos transistor

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- Number: US 2014/0191178 A1
- Document ID: US20140191178A1
- Status: Published application
- Kind: A1
- Application number: 14/150,592
- Filed: 2014-01-08
- Published: 2014-07-10
- Earliest claimed: 2013-01-08
- Assignees: STMicroelectronics (Rousset) SAS
- Applicants: STMicroelectronics (Rousset) SAS
- Inventors: Philippe Boivin
- Web page: https://patentgrep.com/patent/US20140191178A1

## CPC

- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10B 63/34: {of the vertical channel field-effect transistor type}
- H10D 30/0411: {of FETs having floating gates}
- H10D 30/0413: {of FETs having charge-trapping gate insulators, e.g. MNOS transistors}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/683: {programmed by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling}
- H10D 30/689: {Vertical floating-gate IGFETs}
- H10D 30/693: {Vertical IGFETs having charge trapping gate insulators}
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10D 64/037: {comprising charge-trapping insulators}
- H10P 14/24: using chemical vapour deposition [CVD]
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3456: {Polycrystalline}
- H10P 32/1406: {by ion implantation}
- H10P 32/1414: {the applied layer being silicon, silicide or SIPOS, e.g. polysilicon or porous silicon}
- H10P 32/171: {being group IV material}
- H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)}
- H10D 62/122: {oriented at angles to substrates, e.g. perpendicular to substrates}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

The disclosure relates to a method of fabricating a vertical MOS transistor, comprising the steps of: forming, above a semiconductor surface, a conductive layer in at least one dielectric layer; etching a hole through at least the conductive layer, the hole exposing an inner lateral edge of the conductive layer and a portion of the semiconductor surface; forming a gate oxide on the inner lateral edge of the conductive layer and a bottom oxide on the portion of the semiconductor surface; forming an etch-protection sidewall on the lateral edge of the hole, the sidewall covering the gate oxide and an outer region of the bottom oxide, leaving an inner region of the bottom oxide exposed; etching the exposed inner region of the bottom oxide until the semiconductor surface is reached; and depositing a semiconductor material in the hole.

## Claims

### Claim 1

A method, comprising:
forming a vertical MOS transistor, the forming of the MOS transistor including:
forming, above a semiconductor surface, a dielectric layer, a conductive layer in the dielectric layer;
etching a hole through the conductive layer, the hole exposing an inner lateral edge of the conductive layer and a portion of the semiconductor surface;
forming a gate dielectric on the inner lateral edge of the conductive layer and a bottom dielectric on the portion of the semiconductor surface;
forming an etch-protection semiconductor sidewall on a lateral edge of the hole, the sidewall covering the gate dielectric and an outer region of the bottom dielectric, leaving an inner region of the bottom dielectric exposed;
etching the exposed inner region of the bottom dielectric until the semiconductor surface is reached; and
depositing a semiconductor material in the hole.

### Claim 2 (depends on 1)

The method according to claim 1, further comprising forming, in the semiconductor surface, a doped region including dopants of a first conductivity type.

### Claim 3 (depends on 2)

The method according to claim 2, further comprising forming a conduction terminal of the transistor by diffusing the dopants from the doped region into the semiconductor material in the hole.

### Claim 4 (depends on 2)

The method according to claim 2 wherein the forming of the transistor further includes doping the etch-protection semiconductor sidewall with dopants of a second conductivity type.

### Claim 5 (depends on 1)

The method according to claim 1, further comprising:
implanting dopants into the top surface of the semiconductor material; and
diffusing the dopants into the hole to form a conduction terminal of the transistor.

### Claim 6 (depends on 1)

The method according to claim 1, further comprising, after forming the gate dielectric:
forming a charge storage layer covering the gate dielectric; and
forming a tunnel dielectric layer covering the charge storage layer.

### Claim 7

A transistor, comprising:
a substrate;
a first dielectric on the substrate;
a conductive layer in the first dielectric ;
a hole through the conductive layer, the hole exposing an inner lateral edge of the conductive layer and a portion of a surface of the substrate;
a gate dielectric on the inner lateral edge of the conductive layer;
a first semiconductor material in the hole;
an etch-protection semiconductor sidewall on a lateral edge of the hole, between the gate dielectric and the first semiconductor material; and
a bottom dielectric having an outer region between a bottom of the etch-protection sidewall and the surface.

### Claim 8 (depends on 7)

The transistor according to claim 7, further comprising a region in the surface including dopants of a first conductivity type.

### Claim 9 (depends on 8)

The transistor according to claim 8 wherein the etch-protection semiconductor sidewall is a second semiconductor material including dopants of a second conductivity type.

### Claim 10 (depends on 7)

The transistor according to claim 7, further comprising a charge storage layer and a tunnel dielectric layer between the gate dielectric and the etch-protection sidewall.

### Claim 11

A device, comprising:
a substrate;
a first doped layer in the substrate;
a first dielectric layer on the first doped layer;
a second dielectric layer on the first dielectric layer;
a conductive layer in the second dielectric layer;
a third dielectric layer on the second dielectric layer and on the conductive layer;
an opening through the third dielectric layer, the conductive layer, and the first dielectric layer, the opening exposing a surface of the first doped layer, sidewalls of the opening including portions of the first and third dielectric layer and the conductive layer;
a first dielectric region at an intersection of the surface of the first doped layer and a first sidewall of the opening;
a second dielectric region at an intersection of the surface of the first doped layer and a first sidewall of the opening;
a third dielectric region on the portion of the sidewall that is the conducive layer;
a protective sidewall in the opening and on the first, second, and third dielectric regions;
a semiconductor material in the opening in contact with the surface of the first doped layer, the material having a first dopant concentration adjacent to the first doped layer and a second dopant concentration spaced from the first dopant concentration by the third dielectric region.

### Claim 12 (depends on 11)

The device of claim 11, further comprising a charge storage layer in the opening adjacent to the third region and separated from the semiconductor material by the protective sidewall.

### Claim 13 (depends on 12)

The device of claim 12, further comprising an dielectric layer between the charge storage layer and the protective sidewall.

### Claim 14 (depends on 11)

The device of claim 11 wherein the semiconductor material includes a first portion in the opening and a second portion on top of the opening that is wider than the first portion in the opening.

### Claim 15 (depends on 14)

The device of claim 14, further comprising a storage element formed on top of the second portion of the semiconductor material.

### Claim 16 (depends on 15)

The device of claim 15 wherein the storage element includes a first electrode on the second portion of the semiconductor material, a resistive memory region on the first electrode, and a second electrode on the resistive memory region.