# US 2014/0191115 A1 · Spad sensor circuit with biasing circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0191115 A1 - Document ID: US20140191115A1 - Status: Published application - Kind: A1 - Application number: 14/150,346 - Filed: 2014-01-08 - Published: 2014-07-10 - Earliest claimed: 2013-01-09 - Assignees: The University Court of the Uniersity of Edinburgh; STMicroelectronics (Research & Development) Limited - Applicants: The University Court of the Uniersity of Edinburgh; Stmicroelectronics (Research & Development) Limited - Inventors: Eric Alexander Garner Webster; Robert K. Henderson - Web page: https://patentgrep.com/patent/US20140191115A1 ## CPC - H10F 30/225: the potential barrier working in avalanche mode, e.g. avalanche photodiodes - H10F 39/803: {Pixels having integrated switching, control, storage or amplification elements} - H10F 77/959: {for devices working in avalanche mode} - H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION ## Abstract A deep SPAD structure uses the substrate as the anode terminal of its multiplication p-n junction. A bias voltage for the SPAD (in excess of the SPAD's breakdown voltage) is coupled to the SPAD's cathode terminal. The bias voltage is generated by a charge pump circuit which is also integrated on the substrate. The charge pump circuit is configured to isolate the bias voltage on the cathode terminal. A triple well CMOS process is used to isolate the transistors of the charge pump circuit from the substrate. ## Claims ### Claim 1 A sensor circuit, comprising: a single photon avalanche diode (SPAD) configured to receive a bias voltage; a charge pump operable to generate said bias voltage from a first voltage and a second voltage, said bias voltage being higher than a breakdown voltage of the SPAD, each of said first voltage and said second voltage being lower than the breakdown voltage of the SPAD; wherein said charge pump is operable to isolate the bias voltage on an electrode of the SPAD, thereby biasing said SPAD. ### Claim 2 (depends on 1) The sensor circuit as claimed in claim 1, wherein said charge pump and said SPAD are integrated on a common substrate. ### Claim 3 (depends on 2) The sensor circuit as claimed in claim 2, wherein said common substrate forms one half of a multiplication junction for the SPAD. ### Claim 4 (depends on 2) The sensor circuit as claimed in claim 2, wherein said charge pump is operable to stack the first and second voltages on one of its nodes so as to generate said bias voltage. ### Claim 5 (depends on 4) The sensor circuit as claimed in claim 4, wherein said charge pump comprises at least one diode at its output, isolated from said substrate, with said first and second voltages being stacked on said diode. ### Claim 6 (depends on 5) The sensor circuit as claimed in claim 5, wherein said first and second voltages are stacked such that a parasitic junction breakdown voltage limit is not exceeded. ### Claim 7 (depends on 5) The sensor circuit as claimed in claim 5, wherein said at least one diode is integrated within the SPAD. ### Claim 8 (depends on 7) The sensor circuit as claimed in claim 7, wherein said diode comprises a diode implant formed within an implant which forms one half of a multiplication junction of the SPAD. ### Claim 9 (depends on 5) The sensor circuit as claimed in claim 5, wherein said diode is comprised within a separate well implant. ### Claim 10 (depends on 5) The sensor circuit as claimed in claim 5, wherein said first voltage is applied to the electrode of the SPAD via said diode; said circuit comprising a capacitor operable to DC-isolate output devices from said bias voltage, wherein said second voltage is applied to the electrode of the SPAD via said capacitor. ### Claim 11 (depends on 5) The sensor circuit as claimed in claim 5, wherein said node on which said voltage is stacked in order to generate the bias voltage comprises a drain or source implant of a MOSFET device configured as said diode. ### Claim 12 (depends on 11) The sensor circuit as claimed in claim 11, wherein said first and second voltages are stacked such that a transistor gate oxide voltage limit of the MOSFET device is not exceeded. ### Claim 13 (depends on 11) The sensor circuit as claimed in claim 11, wherein said charge pump comprises a plurality of MOSFET devices isolated from said substrate in a well implant. ### Claim 14 (depends on 13) The sensor circuit as claimed in claim 13, wherein the charge pump comprises one of NMOS transistors isolated from the substrate inside a p-well or PMOS transistors isolated from the substrate inside an n-well. ### Claim 15 (depends on 1) The sensor circuit as claimed in claim 1, wherein said charge pump is operable in alternate phases of charging a capacitance with said first voltage and outputting the voltage stored on said capacitance in series with said second voltage. ### Claim 16 (depends on 15) The sensor circuit as claimed in claim 15, wherein the charge pump comprises two capacitances and four MOSFET devices, a first two of said MOSFET devices being operable to selectively connect the first voltage to respective ones of said capacitances and a second two of said MOSFET devices acting as diodes being operable to isolate the voltage on the SPAD cathode from the output of said output stage. ### Claim 17 (depends on 1) The sensor circuit as claimed in claim 1, wherein the charge pump is enabled at periodic intervals. ### Claim 18 (depends on 17) The sensor circuit as claimed in claim 17, wherein said periodic intervals are selected to be sufficient to counteract leakage from the SPAD cathode. ### Claim 19 (depends on 17) The sensor circuit as claimed in claim 17, further comprising a circuit configured to sense that the SPAD has triggered and, on sensing the trigger, actively enable the charge pump. ### Claim 20 (depends on 19) The sensor circuit as claimed in claim 19, further comprising an additional circuit configured to enable a correlated emission source. ### Claim 21 (depends on 1) The sensor circuit as claimed in claim 1, wherein the bias voltage is stored on a capacitance of the SPAD, said capacitance comprising one of a junction capacitance, a coupling capacitance, and a parasitic capacitance. ### Claim 22 (depends on 1) The sensor circuit as claimed in claim 1, wherein said charge pump isolates the bias voltage on a cathode of the SPAD. ### Claim 23 (depends on 1) The sensor circuit as claimed in claim 1, wherein said second voltage is provided by a periodic clock signal. ### Claim 24 (depends on 23) The sensor circuit as claimed in claim 23, wherein said charge pump is double-sided with said second voltage being provided by two non-overlapping periodic clock signals, the charge pump operable to pump on positive and negative edges of one of said clock signals. ### Claim 25 (depends on 1) The sensor circuit as claimed in claim 1, wherein said charge pump provides a biasing voltage for a further transistor, connected between said charge pump and a cathode of the SPAD, said further transistor being configured to operate as a quenching resistor. ### Claim 26 (depends on 25) The sensor circuit as claimed in claim 25, wherein said further transistor is provided within a well implant comprised within said SPAD. ### Claim 27 (depends on 1) The sensor circuit as claimed in claim 1, further comprising: a plurality of SPAD's; a plurality of charge pumps coupled to the plurality of SPAD's; and an additional charge pump operable to generate said first voltage for application to the plurality of charge pumps. ### Claim 28 (depends on 27) The sensor circuit as claimed in claim 27, wherein each SPAD is connected to a dedicated charge pump.