# US 2014/0190543 A1 · Wafer scale thermoelectric energy harvester

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- Number: US 2014/0190543 A1
- Document ID: US20140190543A1
- Status: Published application
- Kind: A1
- Application number: 13/736,783
- Filed: 2013-01-08
- Published: 2014-07-10
- Earliest claimed: 2013-01-08
- Assignees: Analog Devices, Inc.
- Inventors: Baoxing CHEN
- Web page: https://patentgrep.com/patent/US20140190543A1

## CPC

- H10N 19/101: {Multiple thermocouples connected in a cascade arrangement}
- H10N 10/17: characterised by the structure or configuration of the cell or thermocouple forming the device
- H10N 19/00: Integrated devices, or assemblies of multiple devices, comprising at least one thermoelectric or thermomagnetic element covered by groups H10N10/00 - H10N15/00
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

An integrated circuit may include a substrate and a dielectric layer formed over the substrate. A plurality of p-type thermoelectric elements and a plurality of n-type thermoelectric elements may be disposed within the dielectric layer. The p-type thermoelectric elements and the n-type thermoelectric elements may be connected in series while alternating between the p-type and the n-type thermoelectric elements.

## Claims

### Claim 1

An integrated circuit, comprising:
a substrate;
a dielectric layer formed over the substrate;
a plurality of p-type thermoelectric elements disposed within the dielectric layer; and
a plurality of n-type thermoelectric elements disposed within the dielectric layer, wherein the p-type thermoelectric elements and the n-type thermoelectric elements are connected in series while alternating between the p-type and the n-type thermoelectric elements.

### Claim 2 (depends on 1)

The integrated circuit of claim 1, further comprising a thermal contact layer disposed above the p-type thermoelectric elements and the n-type thermoelectric elements.

### Claim 3 (depends on 1)

The integrated circuit of claim 1, wherein each thermoelectric element has a top and a bottom, wherein the top of one thermoelectric element is connected to the top of a first adjacent thermoelectric element and the bottom of the one thermoelectric element is connected to the bottom of a second adjacent thermoelectric element.

### Claim 4 (depends on 3)

The integrated circuit of claim 3, wherein the thermoelectric elements are connected via interconnects and a barrier metal is included between each interconnect and the thermoelectric elements.

### Claim 5 (depends on 1)

The integrated circuit of claim 1, wherein each p-type thermoelectric element is adjacent to only n-type thermoelectric elements.

### Claim 6 (depends on 1)

The integrated circuit of claim 1, wherein the dielectric layer is a polyimide layer.

### Claim 7 (depends on 6)

The integrated circuit of claim 6, further comprising a thermal contact layer above the polyimide layer.

### Claim 8 (depends on 7)

The integrated circuit of claim 7, further comprising an aluminum nitride layer between the polyimide layer and the thermal contact layer.

### Claim 9 (depends on 1)

The integrated circuit of claim 1, wherein the p-type thermoelectric elements and the n-type thermoelectric elements have higher thermal conductivity than the thermal conductivity of the dielectric layer.

### Claim 10 (depends on 1)

The integrated circuit of claim 1, wherein the dielectric layer is an electric insulator and has a lower thermal conductivity than the substrate and the thermoelectric elements.

### Claim 11

An integrated circuit, comprising:
a substrate;
a plurality of p-type and n-type thermoelectric elements disposed above the substrate and connected in series while alternating between the p-type and the n-type thermoelectric elements; and
a cap above the substrate to enclose the thermoelectric elements between the cap and the substrate.

### Claim 12 (depends on 11)

The integrated circuit of claim 11, wherein a low pressure is provided around the thermoelectric elements and between the cap and the substrate.

### Claim 13 (depends on 11)

The integrated circuit of claim 11, further comprising a thermal contact layer disposed above the cap.

### Claim 14 (depends on 11)

The integrated circuit of claim 11, wherein each thermoelectric element has a top and a bottom, wherein the top of one thermoelectric element is connected to the top of a first adjacent thermoelectric element and the bottom of the one thermoelectric element is connected to the bottom of a second adjacent thermoelectric element.

### Claim 15 (depends on 14)

The integrated circuit of claim 14, wherein the thermoelectric elements are connected via interconnects and a barrier metal is included between each interconnect and the thermoelectric elements.

### Claim 16 (depends on 11)

The integrated circuit of claim 11, wherein each p-type thermoelectric element is adjacent to only n-type thermoelectric elements.

### Claim 17

A thermoelectric energy harvester, comprising:
a substrate;
an array of thermoelectric couples disposed above the substrate and connected in series via interconnects, each thermoelectric couple including a first element of a p-type material and a second element of an n-type material, the first element and the second element coupled via the interconnect at one end; and
a dielectric provided between the first elements and the second elements to electrically isolate the first and the first elements and the second elements.

### Claim 18 (depends on 17)

The thermoelectric energy harvester of claim 17, further comprising a thermal contact layer disposed above the dielectric.

### Claim 19 (depends on 18)

The thermoelectric energy harvester of claim 18, further comprising an aluminum nitride layer between the dielectric and the thermal contact layer.

### Claim 20 (depends on 17)

The thermoelectric energy harvester of claim 17, further comprising a barrier metal between each interconnect and the first and second elements.