Optimization of packet processing by delaying a processor from entering an idle state

A computer-readable storage medium storing computer-executable instructions that, when executed by a processor, cause the processor to perform operations, comprising:

• receiving a network packet for processing at a first pipeline stage in a plurality of pipeline stages, the first pipeline stage in the plurality of pipeline stages associated with a queue of network packets to be processed by the processor;
• processing the network packet;
• upon completion of processing the network packet, determining a queue length of a particular queue associated with an upstream pipeline stage, the upstream pipeline stage configured to process the network packet after the first pipeline stage;
• and
• if the queue length exceeds a threshold value, delaying the processor from entering an idle state for a duration of time.

A system, comprising:

• a processor;
• and
• a memory device including instructions that, when executed by the processor, cause the processor to:
• determine a processing time for a particular stage of a pipeline, the particular stage included in a plurality of ordered stages;
• determine at least one delay value based at least in part on the determined processing time of a prior stage and a transmission time between the plurality of ordered stages;
• receive a first network packet at the pipeline;
• process the first network packet while the processor is in a processing state;
• and
• remain in the processing state after processing the first network packet for a second time corresponding to the determined delay, wherein a second packet received at the pipeline is able to be processed while the processor is in the processing state during the second time corresponding to the determined delay.