Timing bottleneck analysis across pipelines to guide optimization with useful skew
AssigneeSynopsys, Inc.
InventorAiqun Cao
Life of this patent
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Abstract
Techniques and systems for guiding circuit optimization are described. Some embodiments compute a set of aggregate slacks for a set of chains of logic paths in a circuit design. Each chain of logic paths starts from a primary input or a sequential circuit element that only launches a signal but does not capture a signal and ends at a primary output or a sequential circuit element that only captures a signal but does not launch a signal. Next, the embodiments guide circuit optimization of the circuit design based on the set of aggregate slacks.
Claims18
A method for guiding circuit optimization, the method comprising:
- computing a set of aggregate slacks for a set of chains of logic paths in a circuit design, wherein each chain of logic paths starts from a primary input or a sequential circuit element that only launches a signal but does not capture a signal and ends at a primary output or a sequential circuit element that only captures a signal but does not launch a signal;
- and
- guiding circuit optimization of the circuit design based on the set of aggregate slacks.
A non-transitory computer-readable storage medium storing instructions that, when executed by a computer, cause the computer to perform a method for guiding circuit optimization, the method comprising:
- computing a set of aggregate slacks for a set of chains of logic paths in a circuit design, wherein each chain of logic paths starts from a primary input or a sequential circuit element that only launches a signal but does not capture a signal and ends at a primary output or a sequential circuit element that only captures a signal but does not launch a signal;
- and
- guiding circuit optimization of the circuit design based on the set of aggregate slacks.
An apparatus, comprising:
- a processor;
- and
- a non-transitory storage medium storing instructions that, when executed by the processor, cause the apparatus to perform a method for guiding circuit optimization, the method comprising:
- computing a set of aggregate slacks for a set of chains of logic paths in a circuit design, wherein each chain of logic paths starts from a primary input or a sequential circuit element that only launches a signal but does not capture a signal and ends at a primary output or a sequential circuit element that only captures a signal but does not launch a signal;
- and
- guiding circuit optimization of the circuit design based on the set of aggregate slacks.
Dependencies are inferred from the claim text.