Unit capacitor module, automatic capacitor layout method thereof and automatic capacitor layout device thereof

An automatic capacitor layout method, comprising:

• utilizing a unit capacitor module for generating a first capacitor array, wherein an area of the first capacitor array covers a chip area;
• acquiring a plurality of circuit areas covered by a plurality of circuit blocks in the chip area according to a layout file;
• comparing the area of the first capacitor array and the plurality of circuit areas, for removing areas of the first capacitor array overlapping the plurality of circuit areas, to generate a second capacitor array;
• and
• generating a final layout file according to the layout file and the second capacitor array.

A unit capacitor module for automatic capacitor layout, comprising:

• a capacitor unit;
• at least one first connecting port, coupled to a first side of the capacitor unit;
• at least one second connecting port, coupled to a second side of the capacitor unit;
• at least one third connecting port, coupled to a third side of the capacitor unit;
• and
• at least one fourth connecting port, coupled to a fourth side of the capacitor unit;
• wherein the number of first connecting ports equals the number of second connecting ports, and a distance between a first axis of the unit capacitor module and the first connecting port equals a distance between the first axis of the unit capacitor module and the second connecting port;
• the number of third connecting ports equals the number of fourth connecting ports, and a distance between a second axis of the unit capacitor module and the third connecting port equals a distance between the second axis of the unit capacitor module and the fourth connecting port.

An automatic capacitor layout device, comprising:

• a processing unit;
• and
• a storage unit, for storing a program code instructing the processing unit to execute the following steps:
• utilizing a unit capacitor module for generating a first capacitor array, wherein an area of the first capacitor array covers a chip area;
• acquiring a plurality of circuit areas covered by a plurality of circuit blocks in the chip area according to a layout file;
• comparing the area of the first capacitor array and the plurality of circuit areas, for removing areas of the first capacitor array overlapping the plurality of circuit areas to generate a second capacitor array;
• and
• generating a final layout file according to the layout file and the second capacitor array.

An automatic capacitor layout method, comprising:

• acquiring a chip area and a plurality of circuit areas covered by a plurality of circuit blocks in the chip area according to a layout file;
• comparing the chip area and the plurality of circuit areas, for removing areas in the chip area overlapping the plurality of circuit areas to generate a capacitor area;
• utilizing a unit capacitor module for generating a capacitor array to fill the capacitor area, wherein an area of the capacitor array is smaller than or equal to the capacitor area;
• and
• generating a final layout file according to the layout file and the capacitor array.

An automatic capacitor layout device, comprising:

• a processing unit;
• and
• a storage unit, for storing a program code instructing the processing unit to execute the following steps:
• acquiring a chip area and a plurality of circuit areas covered by a plurality of circuit blocks in the chip area according to a layout file;
• comparing the chip area and the plurality of circuit areas, for removing areas in the chip area overlapping the plurality of circuit areas to generate a capacitor area;
• utilizing a unit capacitor module for generating a capacitor array to fill the capacitor area, wherein an area of the capacitor array is smaller than or equal to the capacitor area;
• and
• generating a final layout file according to the layout file and the capacitor array.