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AssigneeAdvanced Micro Devices, Inc.
InventorsJian Yang, Pingping Shao, Houkun Li, Jerry Su, Chi Tang, Griffin Wang
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A method and apparatus for automated performance verification for integrated circuit design is described herein. The method includes test preparation and automated verification stages. The test preparation stage generates design feature-specific performance tests to meet expected performance goals under certain workloads using optimization approaches and for different design configurations. The automated verification stage is implemented by integrating functional, automated modules into a verification infrastructure. These modules include register transfer level (RTL) simulation, performance evaluation and performance publish modules. The RTL simulation module schedules performance testing jobs, runs a series of performance tests on simulation logic simultaneously and generates performance counters for each functional unit. The performance evaluation module consists of three sub-functions including a functional comparison between actual results and a reference file containing the expected results, performance measurements for throughput, execution time, and latency values, and performance analysis. The performance publish module publishes performance results and analysis reports.
A method for verifying performance of a unit in an integrated circuit, comprising:
A device configured to verify performance of a unit in an integrated circuit, comprising:
A computer readable non-transitory medium including instructions which when executed in a processing system cause the processing system to execute a method for verifying performance of a unit in an integrated circuit, the method comprising the steps of:
Dependencies are inferred from the claim text.