Method, apparatus, and system for efficient pre-silicon debug
AssigneeIntel Corporation
InventorsErez Kohavi, Evgeniy Ainbinder
Life of this patent
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Abstract
Described are method, apparatus, and system for efficient pre-silicon validation of an integrated circuit. The method comprises: analyzing architectural verification environment associated with a hardware description language (HDL) architecture of an integrated circuit; recognizing method calls associated with the architectural verification environment; and generating a list of recognized method calls, the list for being loaded for a debug program to debug the HDL architecture of the integrated circuit.
Claims20
A method comprising:
- analyzing architectural verification environment associated with a hardware description language (HDL) architecture of an integrated circuit;
- recognizing method calls associated with the architectural verification environment;
- and
- generating, by a computing device, a list of recognized method calls, the list for being loaded for a debug program to debug the HDL architecture of the integrated circuit.
A computer executable storage medium having computer executable instructions that, when executed, cause a processor to perform a method comprising:
- analyzing architectural verification environment associated with a hardware description language (HDL) architecture of an integrated circuit;
- recognizing method calls associated with the architectural verification environment;
- and
- generating a list of recognized method calls, the list for being loaded for a debug program to debug the HDL architecture of the integrated circuit.
A computer system comprising:
- a memory unit;
- a processor, coupled to the memory unit, the processor operable to:
- analyze architectural verification environment associated with a hardware description language (HDL) architecture of an integrated circuit;
- recognize method calls associated with the architectural verification environment;
- and
- generate a list of recognized method calls, the list for being loaded for a debug program to debug the HDL architecture of the integrated circuit;
- and
- a display unit to display debug information, generated by the processor, in a graphical user interface (GUI).
Dependencies are inferred from the claim text.