Identifying circuit elements for selective inclusion in speed-push processing in an integrated circuit, and related circuit systems, apparatus, and computer-readable media

A speed-push mask processing circuit configured to:

• analyze a circuit design comprising a plurality of cells to which a speed-push mask is applied;
• identify at least one of the plurality of cells as having performance margin based on analyzing the circuit design;
• and
• alter the speed-push mask to indicate that the at least one of the plurality of cells having performance margin is to be fabricated as a non-speed-pushed cell by modifying at least one of a channel width, a channel length, or a rate oxide thickness of the non-speed-pushed cell.

A speed-push mask processing circuit, comprising:

• a means for analyzing a circuit design comprising a plurality of cells to which a speed-push mask is applied;
• a means for identifying at least one of the plurality of cells as having performance margin based on analyzing the circuit design;
• and
• a means for altering the speed-push mask to indicate that the at least one of the plurality of cells having performance margin is to be fabricated as a non-speed-pushed cell by modifying at least one of a channel width, a channel length, or a gate oxide thickness of the non-speed-pushed cell.

A non-transitory computer-readable medium, having stored thereon computer-executable instructions to cause a processor to implement a method comprising:

• analyzing a circuit design comprising a plurality of cells to which a speed-push mask is applied;
• identifying at least one of the plurality of cells as having performance margin based on analyzing the circuit design;
• and
• altering the speed-push mask to indicate that the at least one of the plurality of cells having performance margin is to be fabricated as a non-speed-pushed cell by modifying at least one of a channel width, a channel length, or a gate oxide thickness of the non-speed-pushed cell.

A method for creating a speed-push mask, comprising:

• analyzing, by a processor, a circuit design comprising a plurality of cells;
• identifying, by the processor, at least one of the plurality of cells below a performance threshold based on analyzing the circuit design;
• and
• creating, by the processor, a speed-push mask indicating that the at least one of the plurality of cells below the performance threshold is to be fabricated as a speed-pushed cell by modifying at least one of a channel width, a channel length, or a gate oxide thickness, of the speed-pushed cell.

A speed-push mask processing circuit configured to:

• analyze a circuit design comprising a plurality of cells;
• identify at least one of the plurality of cells below a performance threshold based on analyzing the circuit design;
• and
• create a speed-push mask indicating that the at least one of the plurality of cells below the performance threshold is to be fabricated as a speed-pushed cell by modifying at least one of a channel width, a channel length, or a gate oxide thickness of the seed-pushed cell.

A speed-push mask processing circuit, comprising:

• a means for analyzing a circuit design comprising a plurality of cells;
• a means for identifying at least one of the plurality of cells below a performance threshold based on analyzing the circuit design;
• and
• a means for creating a speed-push mask indicating that the at least one of the plurality of cells below the performance threshold is to be fabricated as a speed-pushed cell by modifying at least one of a channel width, a channel length, or a gate oxide thickness of the seed-pushed cell.

A non-transitory computer-readable medium, having stored thereon computer-executable instructions to cause a processor to implement a method comprising:

• analyzing a circuit design comprising a plurality of cells;
• identifying at least one of the plurality of cells below a performance threshold based on analyzing the circuit design;
• and
• creating a speed-push mask indicating that the at least one of the plurality of cells below the performance threshold is to be fabricated as a speed-pushed cell by modifying at least one of a channel width, a channel length, or a gate oxide thickness of the speed-pushed cell.