Semiconductor test system and method
AssigneeTexas Instruments Incorporated
InventorLee D. Whetsel
Life of this patent
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Abstract
A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test.
Claims6
An integrated circuit comprising:
- A. input pads;
- B. output pads;
- C. core circuitry coupled between the input pads and the output pads;
- D. output circuitry coupled between the core circuitry and an output, the output circuitry including:
- i. a tri-state buffer having a core input lead coupled to a core output lead of the core circuitry, a data output lead connected to an output pad and an tristate enable input lead;
- ii. comparator circuitry having a core input coupled to the core output lead, a response input connected to the output pad, and an enable input lead connected to the tristate enable input of the tri-state buffer;
- and
- iii. multiplex circuitry having inputs connected to core output leads of the core circuitry, a core select input, and a selected core output connected to the core input of the compare circuitry.
Dependencies are inferred from the claim text.