Asynchronous programmable jtag-based interface to debug any system-on-chip states, power modes, resets, clocks, and complex digital logic

A method to asynchronously debug a core logic, the core logic comprising a central processing unit, a bus, and a functional clock, the method comprising:

• executing, by an intelligence unit, a test program on a joint test action group (JTAG) debugger in conjunction with a JTAG test action port (TAP) controller using a test clock, the test program to be run on the core logic through a JTAG interface in real time;
• sending, by the test program, a user-defined instruction to the JTAG debugger, wherein the user-defined instruction causes a write select register to be enabled in a write interface;
• initiating, by the test program, a first write operation to the core logic, the first write operation to occur through a side channel between the write interface and the core logic, wherein the JTAG debugger and JTAG TAP controller are not part of the side-channel transaction;
• sending, by the intelligence unit, a predetermined number of idle states to the core logic, wherein the intelligence unit uses the JTAG debugger, the TAP controller, and the JTAG interface to send the idle states to the core logic;
• and
• initiating, by the intelligence unit, a second write operation to the core logic, wherein the second write operation is sent through the side channel.

A method to asynchronously debug a core logic, the core logic comprising a central processing unit, a bus, and a functional clock, the method comprising:

• executing, by an intelligence unit, a test program on a joint test action group (JTAG) debugger in conjunction with a JTAG test action port (TAP) controller using a test clock, the test program to be run on the core logic through a JTAG interface in real time;
• sending, by the test program, a user-defined instruction to the JTAG debugger, wherein the user-defined instruction causes a read select register to be enabled in a read interface;
• initiating, by the test program, a first read operation from the core logic, the first read operation to occur through a side channel between the read interface and the core logic, wherein the JTAG debugger and JTAG TAP controller are not part of the side-channel transaction;
• sending, by the intelligence unit, a predetermined number of idle states to the core logic, wherein the intelligence unit uses the JTAG debugger, the TAP controller, and the JTAG interface to send the idle states to the core logic;
• and
• initiating, by the intelligence unit, a second read operation from the core logic, wherein the second read operation is sent through the side channel.